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1.发明授权Optical system for multi-part differential particle discrimination and an apparatus using the same 失效用于多部分差分粒子鉴别的光学系统及其使用的装置公开(公告)号：US06507400B1
公开(公告)日：2003-01-14
申请号：US09507429
申请日：2000-02-19
IPC分类号： G01N2100
CPC分类号： G01N21/51 , G01N15/1456 , G01N21/05 , G01N2015/1006 , G01N2015/1037 , G01N2015/1486 , G01N2015/149 , G01N2021/0346
摘要： The present invention relates to an optical system for an apparatus for multi-part differential particle discrimination to facilitate analysis, classification, and sorting of various fluid components for presentation. The optical system is characterized by one or more of the following: a synchronized illumination beam and flow cell conduit, a flow cell arrangement to control back reflection, and light sensor arrangement to particularly gather a specific range of light scatter, such specific range of light scatter directly corresponding to at least one type of particle capable of being identified by the apparatus.
摘要翻译： 本发明涉及一种用于多部分差分粒子鉴别的装置的光学系统，以便于用于呈现的各种流体部件的分析，分类和分类。 光学系统的特征在于以下一个或多个：同步照明光束和流动池导管，用于控制反射反射的流动池装置和光传感器装置，以特别收集特定范围的光散射，这种特定范围的光 直接对应于能够被该装置识别的至少一种类型的颗粒。
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公开(公告)号：US20060248174A1
公开(公告)日：2006-11-02
申请号：US11118150
申请日：2005-04-29
申请人： Russell Schultz , Jean-Charles Pina
发明人： Russell Schultz , Jean-Charles Pina
IPC分类号： G06F15/177
CPC分类号： G06F1/266 , G06F2213/0042
摘要： The disclosure is directed to a computational device including functional circuitry, a transceiver interface that is accessible to the functional circuitry, and a universal serial bus transceiver that is accessible to the transceiver interface and that is configured to couple to a universal serial bus compatible media. The transceiver interface is configured to provide a first set of configuration data including a first power setting to a host device via the universal serial bus transceiver. The universal serial bus transceiver is configured to electrically disconnect from and electrically reconnect to the universal serial bus media in response to a suspension signal. The transceiver interface is also configured to provide a second set of configuration data including a second power setting after electrically reconnecting.
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公开(公告)号：US06646742B1
公开(公告)日：2003-11-11
申请号：US09507431
申请日：2000-02-19
申请人： Mervin L. Gangstead , Wieland E. von Behrens , James R. Boyd , Jean-Charles Pina , Jerry B. West
发明人： Mervin L. Gangstead , Wieland E. von Behrens , James R. Boyd , Jean-Charles Pina , Jerry B. West
IPC分类号： G01N2100
CPC分类号： G01N15/1404 , G01N15/0205 , G01N21/532 , G01N2015/1413 , G01N2015/149
摘要： The present invention relates to an optical system for an apparatus for multi-part differential particle discrimination to facilitate analysis, classification, and sorting of various fluid components for presentation. The optical system is characterized by one or more of the following: a synchronized illumination beam and flow cell conduit, a flow cell arrangement to control back reflection, and light sensor arrangement to particularly gather a specific range of light scatter, such specific range of light scatter directly corresponding to at least one type of particle capable of being identified by the apparatus.
摘要翻译： 本发明涉及一种用于多部分差分粒子鉴别的装置的光学系统，以便于用于呈现的各种流体部件的分析，分类和分类。 光学系统的特征在于以下一个或多个：同步照明光束和流动池导管，用于控制反射反射的流动池装置和光传感器装置，以特别收集特定范围的光散射，这种特定范围的光 直接对应于能够被该装置识别的至少一种类型的颗粒。
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4.发明授权Use of NAND flash for hidden memory blocks to store an operating system program 有权使用NAND闪存隐藏内存块来存储操作系统程序公开(公告)号：US07302560B2
公开(公告)日：2007-11-27
申请号：US11728681
申请日：2007-03-26
CPC分类号： G06F12/1433 , G06F2212/2022
摘要： A memory device has a plurality of memory blocks utilized to store data. One of the blocks is used as a hidden memory block to store an operating system program, instead of data. The hidden memory block is designated as a bad block so that data will not be written into the hidden memory block, but a tag associated with the hidden memory block identifies that the hidden memory block contains the operating system program.
摘要翻译： 存储器件具有用于存储数据的多个存储器块。 其中一个块用作隐藏的内存块来存储操作系统程序，而不是数据。 隐藏的存储器块被指定为坏块，使得数据不会被写入隐藏的存储器块，但是与隐藏的存储器块相关联的标签识别出隐藏的存储器块包含操作系统程序。
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5.发明授权Flexible memory interface system for independently processing different portions of an instruction 有权灵活的存储器接口系统，用于独立处理指令的不同部分公开(公告)号：US09547623B2
公开(公告)日：2017-01-17
申请号：US10865585
申请日：2004-06-10
申请人： Steve Vu , Jean Charles Pina
发明人： Steve Vu , Jean Charles Pina
CPC分类号： G06F13/4234 , G06F13/1668 , G06F2213/0038
摘要： A flexible memory interface system includes a control module, instruction memory, a command processing unit, an address processing unit, and a data processing unit. The control module controls storing and retrieving of a command portion, an addressing portion, and data of an instruction to access memory to and from the instruction memory and the command processing unit, the address processing unit, and the data processing unit, respectively. The command processing unit is operably coupled to process a command portion of an instruction to access memory. The address processing unit is operably coupled to process an addressing portion of the instruction to access the memory. The data processing unit is operably coupled to process data conveyance to or from the external memory based on the instruction to access the memory.
摘要翻译： 灵活的存储器接口系统包括控制模块，指令存储器，命令处理单元，地址处理单元和数据处理单元。 控制模块控制命令部分，寻址部分的存储和获取，以及分别向指令存储器和命令处理单元，地址处理单元和数据处理单元访问存储器的指令的数据。 命令处理单元可操作地耦合以处理访问存储器的指令的命令部分。 地址处理单元可操作地耦合以处理指令的寻址部分以访问存储器。 数据处理单元可操作地耦合以基于访问存储器的指令来处理到外部存储器或从外部存储器传送数据。
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公开(公告)号：US08536799B1
公开(公告)日：2013-09-17
申请号：US13077483
申请日：2011-03-31
申请人： Robert T. Grisamore , Firas S. Azrai , Mohit Sood , John L. Melanson , Eric J. King , Jean-Charles Pina
发明人： Robert T. Grisamore , Firas S. Azrai , Mohit Sood , John L. Melanson , Eric J. King , Jean-Charles Pina
IPC分类号： H05B37/02
CPC分类号： H05B33/0815 , G01R19/0046 , H05B33/0848 , H05B37/0218 , H05B37/0263 , Y02B20/346
摘要： In at least one embodiment, a lighting system receives an input signal, such as a supply voltage, that can be affected by a dimmer. The supply voltage can be affected by a dimmer when, for example, a dimmer phase cut (i.e. chopped) the supply voltage. A dimmer detection system of the lighting system determines if a dimmer is affecting the supply voltage. In at least one embodiment, the dimmer detection system also determines a type of the dimmer, such as detecting if the dimmer is a leading edge or trailing edge dimmer. In at least one embodiment, the dimmer detection system provides dimmer type data to one or more other circuits such as a switching power converter controller. The one or more other circuits utilize the dimmer type data to affect their operation.
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7.发明授权公开(公告)号：US08165835B1
公开(公告)日：2012-04-24
申请号：US12259112
申请日：2008-10-27
申请人： Rahul Singh , Dale Brummel , Hang Liu , Robert Leon Gorsegner , Edwin De Angel , Jean Charles Pina
发明人： Rahul Singh , Dale Brummel , Hang Liu , Robert Leon Gorsegner , Edwin De Angel , Jean Charles Pina
CPC分类号： G01R21/1331
摘要： A power measurement and calibration system provides power and line frequency measurements by using a bandpass filter having complex voltage and current outputs from which real and imaginary power components can be determined. Calibration of the filter may be omitted if a complex wavelet filter is used to implement the bandpass filter and a determination of line frequency can also be provided for downstream use. A processor receiving data from the output of the filter can compute real and imaginary power, power factor and the line frequency. The filter may be implemented by a processor executing program instructions, or a digital circuit implementing the filter and optionally a CORDIC rotator for computing the current-to-voltage phase relationship can provide input to the processor for power measurement and calibration of the sample rate to line frequency relationship and for other uses.
摘要翻译： 功率测量和校准系统通过使用具有复数电压和电流输出的带通滤波器来提供功率和线路频率测量，从而可以确定实际和虚拟功率分量。 如果使用复小波滤波器来实现带通滤波器，则也可以省略滤波器的校准，还可以为下游使用提供线路频率的确定。 从滤波器的输出接收数据的处理器可以计算实际功率，虚功率，功率因数和线路频率。 滤波器可以由执行程序指令的处理器或实现滤波器的数字电路和可选地用于计算电流到电压相位关系的CORDIC转子来实现，其可以向处理器提供输入以进行功率测量并将采样率校准到 线频率关系和其他用途。
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8.发明授权Method and apparatus for automatically securing non-volatile (NV) storage in an integrated circuit 有权在集成电路中自动保护非易失性（NV）存储的方法和装置公开(公告)号：US07657722B1
公开(公告)日：2010-02-02
申请号：US11772136
申请日：2007-06-30
IPC分类号： G06F12/00
摘要： A method and apparatus for automatically securing non-volatile (NV) storage in an integrated circuit provides improved resistance to code copying and reverse-engineering attacks. External interfaces that provide read access to the NV storage are be disabled, for a predetermined time after a reset or other initialization signal is received. An internal lock state bit or key is checked as well as an external lock prevent indication. If the lock prevent indication is not received, or the internal lock state bit is already set, then the integrated circuit is operated under a locked condition, in which external access to the NV storage values is prevented. The lock prevent indication may be a signal provided during reset of the integrated circuit on a terminal that is used for another purpose after initialization of the integrated circuit.
摘要翻译： 用于在集成电路中自动保护非易失性（NV）存储的方法和装置提供了改进的对代码复制和逆向工程攻击的抵抗力。 在接收到复位或其他初始化信号之后的预定时间内，禁止提供对NV存储器的读取访问的外部接口。 检查内部锁定状态位或键以及外部锁定防止指示。 如果没有接收到锁定防止指示，或内部锁定状态位已设置，则集成电路在锁定状态下运行，从而防止NV存储值的外部访问。 锁定防止指示可以是在集成电路初始化之后用于另一目的的终端上的集成电路复位期间提供的信号。
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公开(公告)号：US07512720B2
公开(公告)日：2009-03-31
申请号：US11118150
申请日：2005-04-29
IPC分类号： G06F3/00
CPC分类号： G06F1/266 , G06F2213/0042
摘要： The disclosure is directed to a computational device including functional circuitry, a transceiver interface that is accessible to the functional circuitry, and a universal serial bus transceiver that is accessible to the transceiver interface and that is configured to couple to a universal serial bus compatible media. The transceiver interface is configured to provide a first set of configuration data including a first power setting to a host device via the universal serial bus transceiver. The universal serial bus transceiver is configured to electrically disconnect from and electrically reconnect to the universal serial bus media in response to a suspension signal. The transceiver interface is also configured to provide a second set of configuration data including a second power setting after electrically reconnecting.
摘要翻译： 本公开涉及包括功能电路，功能电路可访问的收发器接口以及通信串行总线收发器的计算设备，其可被收发器接口访问并被配置为耦合到通用串行总线兼容介质。 收发器接口被配置为经由通用串行总线收发器向主机设备提供包括第一功率设置的第一组配置数据。 通用串行总线收发器被配置为响应于暂停信号而与通用串行总线介质电连接并电连接到通用串行总线介质。 收发器接口还被配置为提供第二组配置数据，包括电重新连接之后的第二功率设置。
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公开(公告)号：US07203828B2
公开(公告)日：2007-04-10
申请号：US10723909
申请日：2003-11-26
CPC分类号： G06F12/1433 , G06F2212/2022
摘要： A memory device has a plurality of memory blocks utilized to store data. One of the blocks is used as a hidden memory block to store an operating system program, instead of data. The hidden memory block is designated as a bad block so that data will not be written into the hidden memory block, but a tag associated with the hidden memory block identifies that the hidden memory block contains the operating system program.
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