公开(公告)号：US5089725A

公开(公告)日：1992-02-18

申请号：US604842

申请日：1990-10-26

申请人： Pierre Mollier ,  Jean-Paul Nuez ,  Pascal Tannhof

发明人： Pierre Mollier ,  Jean-Paul Nuez ,  Pascal Tannhof

IPC分类号： H03K19/013 ,  H03K19/086

CPC分类号： H03K19/086 ,  H03K19/013

摘要： The base circuit comprises a self-referenced preamplifier (31) of the differential type connected between first and second supply voltages and a push-pull output buffer stage connected between second and third supply voltages. The push-pull output buffer stage comprises a pull-up transistor and a pull-down transistor connected in series with the circuit output node coupled therebetween. These transistors are driven by complementary and substantially simultaneous signals S and S supplied by the preamplifier. Both branches of the preamplifier are tied at a first output node (M). The first branch comprises a logic block performing the desired logic function of the base circuit that is connected through a load rsistor to the second supply voltage. The logic block consists of three parallel-connected input NPN transistors, whose emitters are coupled together at the first output node for NOR operation. The second branch is comprised of a biasing/coupling block connected to the second supply voltage and coupled to the first output node and to the base (B) node of the pull-down transistor. This block ensures both the appropriate polarization of the nodes in DC without the need of external reference voltage generators and a low impedance path for fast signal transmission of the output signal from node M to node B in AC, when input transistors of the logic block are ON. and base nodes. An anti-saturation block (AB), consisting typically of a Schottky Barrier Diode (SBD), is useful to prevent saturation of the pull down transistor (TDN) to further speed up the circuit.

摘要翻译： 基本电路包括连接在第一和第二电源电压之间的差分类型的自参考前置放大器（31）和连接在第二和第三电源电压之间的推挽输出缓冲级。 推挽输出缓冲级包括与耦合在其间的电路输出节点串联连接的上拉晶体管和下拉晶体管。 这些晶体管由前置放大器提供的互补和基本同时的信号S和＆amp; upbar＆S驱动。 前置放大器的两个分支都连接在第一个输出节点（M）上。 第一分支包括执行通过负载晶体管连接到第二电源电压的基本电路的期望逻辑功能的逻辑块。 逻辑块由三个并联的输入NPN晶体管组成，其发射极在第一个输出节点耦合在一起用于NOR运算。 第二分支包括连接到第二电源电压并耦合到第一输出节点和下拉晶体管的基极（B）节点的偏置/耦合模块。 该块在逻辑块的输入晶体管中确保DC中节点的适当极化，而不需要外部参考电压发生器和低阻抗路径，用于在AC中将节点M到节点B的输出信号快速信号传输 上。 和基本节点。 通常由肖特基势垒二极管（SBD）组成的抗饱和块（AB）可用于防止下拉晶体管（TDN）的饱和，从而进一步加速电路。

公开(公告)号：US5010257A

公开(公告)日：1991-04-23

申请号：US493014

申请日：1990-03-13

申请人： Gerard Boudon ,  Pierre Mollier ,  Jean-Paul Nuez ,  Ieng Ong ,  Pascal Tannhof ,  Franck Wallart

发明人： Gerard Boudon ,  Pierre Mollier ,  Jean-Paul Nuez ,  Ieng Ong ,  Pascal Tannhof ,  Franck Wallart

IPC分类号： H03K17/567 ,  H03K5/007 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/0136 ,  H03K19/09448 ,  H03K5/007

摘要： According to the present invention, a CMOS interface circuit (C2) similar to a latch made by two CMOS cross coupled inverters (INV1, INV2) is placed directly on the output node (14) of conventional BICMOS logic circuit (11) operating alone in a partial swing mode. This latch is made of four FETs P5, P6, N8, N9 cross-coupled in a conventional way with the feedback loop connected to said output node (14). The partial voltage swing (VBE to VH-VBE) naturally given by the output bipolar transistors (T1, T2) mounted in a push pull configuration is reinforced to full swing (GND to VH) by the latch at the end of each transition. The state of the output node if forced by the latch because of the high driving capability due to the presence of said output bipolar transistors (T1, T2). As a result, the improved BICMOS logic circuit (D2) has an output signal (S) that ranges within the desired full swing voltage at the output terminal (15). It is a characteristic of this embodiment that the structure of CMOS interface (C2) is always independent of the logic function implemented in the conventional BICMOS logic circuit (11). More generally, the CMOS interface circuit may have various physical implementations, however, it is always comprised of CMOS FETs and it becomes active at least in one of the GND to VBE or (VH-BE) to VH range.

公开(公告)号：US4529896A

公开(公告)日：1985-07-16

申请号：US448135

申请日：1982-12-09

申请人： Michel Grandguillot ,  Pierre Mollier ,  Jean-Paul Nuez

发明人： Michel Grandguillot ,  Pierre Mollier ,  Jean-Paul Nuez

IPC分类号： G11C11/413 ,  G11C8/06 ,  H03K5/151 ,  H03K5/15 ,  H03K19/088 ,  H03K19/20

CPC分类号： G11C8/06 ,  H03K5/1515

摘要： A true/complement generator for generating the complement and true value of weighted address bits, preventing an address decoder from selecting several lines at the same time. It comprises two circuits (1) and (2), the first one providing the true value (.phi.), the second one providing the complement (.phi.) thereof. The means provided for preventing multiple selections from occurring, comprise in the first circuit, a transistor (T11-1) for delaying the rising edge of (.phi.) as long as it is maintained on by the level provided by resistors R11-1 and R10-2 from output .phi.. Transistor T11-2 in the second circuit prevents .phi. from going high as long as it is maintained on by the level provided by R10-1, R11-2 from .phi..

摘要翻译： 用于产生加权地址位的补码和真值的真/补码发生器，防止地址解码器同时选择多个行。 它包括两个电路（1）和（2），第一个提供真实值（phi），第二个提供其补码（phi）。 在第一电路中，包括用于延迟（phi）的上升沿的晶体管（T11-1），只要它被电阻器R11-1和R10提供的电平保持在上，则防止发生多重选择的装置 -2从输出phi。 第二回路中的晶体管T11-2只要保持在来自phi的R10-1，R11-2提供的电平，就能防止phi变高。

公开(公告)号：US4922135A

公开(公告)日：1990-05-01

申请号：US271124

申请日：1988-11-14

申请人： Pierre Mollier ,  Pascal Tannhof

发明人： Pierre Mollier ,  Pascal Tannhof

IPC分类号： H01L27/095 ,  H03K5/02 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0952

CPC分类号： H03K19/09436 ,  H03K19/01721

摘要： The present invention relates to a family of new GaAs MESFET logic circuits including push pull output buffers, which exhibits very strong output driving capability and very low power consumption at fast switching speeds. A 3 way OR/NOR circuit of this invention includes a standard differential amplifier, the first branch of which is controlled by logic input signals. The second branch includes a current switch controlled by a reference voltage. The differential amplifier provides first and second output signals simultaneously and complementary each other. The circuit further includes two push pull output buffers. The first output buffer comprises an active pull up device connected in series with an active pull down device, and the first circuit output signal is available at their common node or at the output terminal. The active pull up device is controlled by a first output signal of the differential amplifier, and the active pull down device is preferably controlled by the second output signal through an intermediate source follower buffer. The second output buffer is of similar structure. The depicted circuit is of the dual phase type. However, if only one phase of the circuit output signal is needed, the output buffer and the intermediate buffer can be eliminated. The number of devices can be even further reduced by eliminating the other remaining intermediate buffer.

公开(公告)号：US5023478A

公开(公告)日：1991-06-11

申请号：US493079

申请日：1990-03-13

申请人： Gerard Boudon ,  Pierre Mollier ,  Seiki Ogura ,  Dominique Omet ,  Pascal Tannhof ,  Franck Wallart

发明人： Gerard Boudon ,  Pierre Mollier ,  Seiki Ogura ,  Dominique Omet ,  Pascal Tannhof ,  Franck Wallart

IPC分类号： H03K19/086 ,  H03F1/30 ,  H03F3/30 ,  H03K17/56 ,  H03K17/567 ,  H03K17/66 ,  H03K19/01 ,  H03K19/013 ,  H03K19/018 ,  H03K19/08

CPC分类号： H03K19/013 ,  H03F1/308 ,  H03F3/3008 ,  H03F3/3071 ,  H03K17/667

摘要： The present invention relates to fast complementary emitter follower drivers/buffers to be used in either a CMOS or pure complementary bipolar environment. The output driver (22) comprises top NPN and bottom PNP output transistors (T1, T2) with a common output node (N) connected therebetween. A terminal (15) is connected to the said output node (N) where the output signal (VOUT) is available. The pair of bipolar output transistors is biased between the first and second supply voltages (VH, GND). The output driver is provided with a voltage translator circuit (S) connected between the base nodes (B1, B2) of the output transistors (T1, T2). Logic signals (IN1, IN2), supplied by a preceding driving circuit (21), are applied to said base nodes. According to the invention, the voltage translator circuit (S) comprises two diodes (D1, D2) connected in series, preferably implemented with a main bipolar transistor having a junction shorted by a diode connected transistor to form a Darlington-like configuration. As a result, the voltage shift VS between the base nodes is selected to have the said output transistors operating at an operating point which ensures minimum delay and power consumption. In a typical bipolar technology, VS is made to be approximately equal to 1.5V. Additional features comprise the connection of a capacitor (C) between the base nodes and resistances (R1, R2) to the base nodes. The preceding driving circuit may be a CMOS logic gate or an ECL logic circuit.

公开(公告)号：US5155572A

公开(公告)日：1992-10-13

申请号：US680490

申请日：1991-04-04

申请人： Dominique Bonneau ,  Myriam Combes ,  Anthony J. Dally ,  Pierre Mollier ,  Seiki Ogura ,  Pascal Tannhof

发明人： Dominique Bonneau ,  Myriam Combes ,  Anthony J. Dally ,  Pierre Mollier ,  Seiki Ogura ,  Pascal Tannhof

IPC分类号： H01L27/06 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732 ,  H01L29/74

CPC分类号： H01L29/74 ,  H01L29/0821

摘要： A vertical isolated-collector PNP transistor structure (58) comprises a P+ region (45), a N region (44) and a P- well region (46) which form the emitter, the base and the collector, respectively. The P- well region is enclosed in a N type pocket comprised of a N+ buried layer (48) and a N reach-through region (47) in contact therewith. The contact regions (46-1, 47-1) to the P- well region (46) and to the N reach-through region (47) are shorted to define a common collector contact (59). In addition, the thickness W of the P- well region (46) is so minimized to allow transistor action of the parasitic NPN transistor formed by N PNP base region (44), P- well region (46) and the N+ buried layer, (48) respectively as the collector, the base and the emitter of said PNP transistor. The PNP transistor structure (67) may be combined with a conventional NPN transistor structure (61).

摘要翻译： 垂直隔离集电极PNP晶体管结构（58）包括分别形成发射极，基极和集电极的P +区（45），N区（44）和P-阱区（46）。 P阱区被包围在与N +掩埋层（48）和N接触区域（47）组成的N型槽中。 到P阱区域（46）和N到达区域（47）的接触区域（46-1,47-1）被短路以限定公共集电极接触件（59）。 此外，P阱区域（46）的厚度W被最小化以允许由N PNP基区（44），P-阱区（46）和N +掩埋层形成的寄生NPN晶体管的晶体管作用， （48）分别作为所述PNP晶体管的集电极，基极和发射极。 PNP晶体管结构（67）可以与传统的NPN晶体管结构（61）组合。

公开(公告)号：US5166552A

公开(公告)日：1992-11-24

申请号：US659404

申请日：1991-03-08

申请人： Anthony G. Aipperspach ,  Gerard Boudon ,  Allan H. Dansky ,  Pierre Mollier ,  Ieng Ong ,  Nghia Phan ,  Biagio Pluchino ,  Steven J. Zier ,  Adrian Zuckerman

发明人： Anthony G. Aipperspach ,  Gerard Boudon ,  Allan H. Dansky ,  Pierre Mollier ,  Ieng Ong ,  Nghia Phan ,  Biagio Pluchino ,  Steven J. Zier ,  Adrian Zuckerman

IPC分类号： H03K19/08 ,  H03K19/013 ,  H03K19/017 ,  H03K19/0944 ,  H03K19/21

CPC分类号： H03K19/013 ,  H03K19/01707 ,  H03K19/09448 ,  H03K19/215

摘要： A multi emitter multi input BICMOS NAND circuit (30) is provided wherein an output node OUT connected to an output terminal (33) is coupled between pull up (31) and pull down (32) blocks. According to one embodiment of the present invention, the pull up block (32) is comprised of a plurality of identical basic cells, each comprised of a CMOS inverter (C31, C32) driving an NPN pull up transistor (T31, T32) mounted as an emitter follower. Logic signals (A31, A32) are applied on the inputs of the inverters (C31, C32), and the inverted signal (A31, A32) is available at the emitter of the emitter follower which corresponds to the output of the cell. All outputs are tied altogether to perform an OR function and are connected to said output terminal (33) to have a multi emitter like circuit. The pull down block (32) in this embodiment is comprised of 2 FETs (F31, F32) serially connected between said output node OUT and a discharge device such as a feedback NFET (Z) the gate of which is connected to said output node OUT. These 2 FETs are for driving a NPN pull down transistor (T), the collector of which is also connected to the output node OUT. The invention includes a number of other embodiments including a feedback inverter embodiment, a parasitic node discharge embodiment, and a BIFET latch embodiment.

公开(公告)号：US4539680A

公开(公告)日：1985-09-03

申请号：US556803

申请日：1983-12-01

申请人： Gerard Boudon ,  Pierre Mollier ,  Gerard Lebesherais

发明人： Gerard Boudon ,  Pierre Mollier ,  Gerard Lebesherais

IPC分类号： H04L25/38 ,  H04L25/45 ,  H04L25/48 ,  H04L25/49 ,  H04J3/06 ,  H04L3/00 ,  H04L25/34

CPC分类号： H04L25/45 ,  H04L25/49

摘要： In the transmitting chip, the bits are serialized and applied to a coding circuit in which bit stream (D) and its complement (D) are transformed into two signals (PH1 and PH2) under the control of a saw-tooth clock signal CK'. Signals (PH1 and PH2) are sent to the receiving chip, wherein they are applied to a decoding circuit which generates two signals (DJ) and (DK) representative of the data bits and a recovered clock signal CLK. The three signals (DJ, DK and CLK) as well as a frame signal (F) are used by a converting and demultiplexing circuit for assembling bytes of parallel data bits.

摘要翻译： 在发送芯片中，将这些比特序列化并应用于编码电路，其中，在锯齿时钟信号CK的控制下，比特流（D）及其补码（＆amp; upbar＆D）被变换成两个信号（PH1和PH2） '。 信号（PH1和PH2）被发送到接收芯片，其中它们被应用于产生表示数据位的两个信号（＆amp; upbar＆D）和（＆amp; upbar＆D）的解码电路和恢复的时钟信号CLK。 三个信号（＆upbar＆D，＆upbar＆D和CLK）以及帧信号（F）由转换和解复用电路用于组合并行数据位的字节。

公开(公告)号：US4394752A

公开(公告)日：1983-07-19

申请号：US276136

申请日：1981-06-22

申请人： Gerard Boudon ,  Bernard Denis ,  Virginie de Grivel ,  Pierre Mollier

发明人： Gerard Boudon ,  Bernard Denis ,  Virginie de Grivel ,  Pierre Mollier

IPC分类号： G11C11/41 ,  G11C11/413 ,  G11C11/415 ,  G11C16/08 ,  G11C17/18 ,  G11C7/00

CPC分类号： G11C17/18 ,  G11C11/415 ,  G11C16/08

摘要： A word line selection circuit includes a conventional Schottky diode decoder and a driver transistor which is connected to a word line. A word line is selected when the transistor is conductive and all associated diodes of the decoder are off. The base current of the driver transistor is defined by a control transistor whose conductivity is opposite to that of the driver transistor and which applies the selection current to the base of the driver transistor. A regulating transistor forms a current mirror with the control transistor to regulate the selection current. A compensation circuit associated with the regulating transistor modulates the collector current of the regulating transistor as a function of the driver transistor factor.

摘要翻译： 字线选择电路包括传统的肖特基二极管解码器和连接到字线的驱动晶体管。 当晶体管导通并且解码器的所有相关二极管关闭时，选择字线。 驱动晶体管的基极电流由与驱动晶体管的导通性相反的控制晶体管限定，并将选择电流施加到驱动晶体管的基极。 调节晶体管与控制晶体管形成电流镜以调节选择电流。 与调节晶体管相关联的补偿电路根据驱动晶体管因素调制调节晶体管的集电极电流。

公开(公告)号：US4988893A

公开(公告)日：1991-01-29

申请号：US075806

申请日：1987-07-20

申请人： Martine Bonneau ,  Gerard Boudon ,  Jean-Claude Le Garrec ,  Pierre Mollier ,  Frank Wallart

发明人： Martine Bonneau ,  Gerard Boudon ,  Jean-Claude Le Garrec ,  Pierre Mollier ,  Frank Wallart

IPC分类号： H03K3/3562 ,  H03K3/356

CPC分类号： H03K3/356017 ,  H03K3/356113

摘要： The invention provides novel implementations of a latch cell in CMOS gate array technology to produce latch dissymmetry and permit a single ended data input. The dissymmetry is produced by increasing the output impedance of the second stage of the latch cell, which can be done, either in a DC or in an AC mode, or even in a mixed version of both modes.