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公开(公告)号：US20110241084A1
公开(公告)日：2011-10-06
申请号：US12750160
申请日：2010-03-30
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/66795 , H01L29/7833 , H01L29/7848
摘要： A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.
摘要翻译： 提供了具有局部应力源的半导体器件，例如PMOS或NMOS器件。 凹槽形成在栅电极的相对侧上。 沿着凹部的底部形成应力诱导区域，在应力诱导区域上形成应力层。 通过具有比应力层更大的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生拉伸应变，并且可以适用于NMOS器件。 通过具有比应力层更小的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生压应变，并且可以适用于PMOS器件。 实施例可以应用于各种类型的基板和半导体器件，例如平面晶体管和finFET。
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公开(公告)号：US07892929B2
公开(公告)日：2011-02-22
申请号：US12173263
申请日：2008-07-15
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/76232
摘要： A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration.
摘要翻译： 提供了一种用于对浅沟槽隔离件的角进行倒角的方法。 优选实施例包括用电介质填充沟槽并使电介质凹陷以暴露邻近衬底表面的沟槽侧壁的一部分。 然后将衬底在氢环境中退火，氢环境通过硅迁移使浅沟槽隔离的角落圆。
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3.发明申请Scaling EOT by Eliminating Interfacial Layers from High-K/Metal Gates of MOS Devices 有权通过消除MOS器件的高K /金属栅极的界面层来缩放EOT公开(公告)号：US20110012210A1
公开(公告)日：2011-01-20
申请号：US12789681
申请日：2010-05-28
申请人： Jeffrey Junhao Xu
发明人： Jeffrey Junhao Xu
IPC分类号： H01L29/78
CPC分类号： H01L29/6659 , H01L21/02052 , H01L21/02315 , H01L21/28194 , H01L21/306 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/7833
摘要： An integrated circuit structure includes a semiconductor substrate, and a phonon-screening layer over the semiconductor substrate. Substantially no silicon oxide interfacial layer exists between the semiconductor substrate and the phonon-screening layer. A high-K dielectric layer is located over the phonon-screening layer. A metal gate layer is located over the high-K dielectric layer.
摘要翻译： 集成电路结构包括半导体衬底和半导体衬底上的声子屏蔽层。 在半导体衬底和声子屏蔽层之间基本上不存在氧化硅界面层。 高K介电层位于声子筛选层上方。 金属栅极层位于高K电介质层的上方。
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公开(公告)号：US20080315348A1
公开(公告)日：2008-12-25
申请号：US11768051
申请日：2007-06-25
申请人： Jeffrey Junhao Xu
发明人： Jeffrey Junhao Xu
IPC分类号： H01L23/482 , H01L29/06
CPC分类号： H01L23/522 , H01L27/0207 , H01L27/10882 , H01L27/11517 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; a first bottom metallization (M1) layer over the semiconductor substrate; a second M1 layer over the first M1 layer, wherein metal lines in the first and the second M1 layer have widths of greater than about a minimum feature size; and vias connecting the first and the second M1 layers.
摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的第一底部金属化（M1）层; 第一M1层上的第二M1层，其中第一和第二M1层中的金属线具有大于约最小特征尺寸的宽度; 以及连接第一和第二M1层的通孔。
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公开(公告)号：US08395195B2
公开(公告)日：2013-03-12
申请号：US12702862
申请日：2010-02-09
IPC分类号： H01L27/085
CPC分类号： H01L29/66795 , H01L29/7853
摘要： An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width.
摘要翻译： 集成电路结构包括在衬底上的衬底和含锗半导体鳍。 含锗半导体翅片具有第一宽度的上部和在上部下方的颈部区域，并且具有小于第一宽度的第二宽度。
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公开(公告)号：US08338259B2
公开(公告)日：2012-12-25
申请号：US12750160
申请日：2010-03-30
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/66795 , H01L29/7833 , H01L29/7848
摘要： A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.
摘要翻译： 提供了具有局部应力源的半导体器件，例如PMOS或NMOS器件。 凹槽形成在栅电极的相对侧上。 沿着凹部的底部形成应力诱导区域，在应力诱导区域上形成应力层。 通过具有比应力层更大的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生拉伸应变，并且可以适用于NMOS器件。 通过具有比应力层更小的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生压应变，并且可以适用于PMOS器件。 实施例可以应用于各种类型的基板和半导体器件，例如平面晶体管和finFET。
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公开(公告)号：US20110193178A1
公开(公告)日：2011-08-11
申请号：US12702862
申请日：2010-02-09
CPC分类号： H01L29/66795 , H01L29/7853
摘要： An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width.
摘要翻译： 集成电路结构包括在衬底上的衬底和含锗半导体鳍。 含锗半导体翅片具有第一宽度的上部和在上部下方的颈部区域，并且具有小于第一宽度的第二宽度。
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公开(公告)号：US07737554B2
公开(公告)日：2010-06-15
申请号：US11768051
申请日：2007-06-25
申请人： Jeffrey Junhao Xu
发明人： Jeffrey Junhao Xu
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L27/0207 , H01L27/10882 , H01L27/11517 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; a first bottom metallization (M1) layer over the semiconductor substrate; a second M1 layer over the first M1 layer, wherein metal lines in the first and the second M1 layer have widths of greater than about a minimum feature size; and vias connecting the first and the second M1 layers.
摘要翻译： 集成电路结构包括：半导体衬底; 半导体衬底上的第一底部金属化（M1）层; 第一M1层上的第二M1层，其中第一和第二M1层中的金属线具有大于约最小特征尺寸的宽度; 以及连接第一和第二M1层的通孔。
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公开(公告)号：US20100015776A1
公开(公告)日：2010-01-21
申请号：US12173263
申请日：2008-07-15
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/76232
摘要： A method for rounding the corners of a shallow trench isolation is provided. A preferred embodiment comprises filling the trench with a dielectric and recessing the dielectric to expose a portion of the sidewalls of the trench adjacent to the surface of the substrate. The substrate is then annealed in a hydrogen ambient, which rounds the corners of the shallow trench isolation through silicon migration.
摘要翻译： 提供了一种用于对浅沟槽隔离件的角进行倒角的方法。 优选实施例包括用电介质填充沟槽并使电介质凹陷以暴露邻近衬底表面的沟槽侧壁的一部分。 然后将衬底在氢环境中退火，氢环境通过硅迁移使浅沟槽隔离的角落圆。
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10.发明授权Scaling EOT by eliminating interfacial layers from high-K/metal gates of MOS devices 有权通过消除MOS器件的高K /金属栅极的界面层来缩放EOT公开(公告)号：US09478637B2
公开(公告)日：2016-10-25
申请号：US12789681
申请日：2010-05-28
申请人： Jeffrey Junhao Xu
发明人： Jeffrey Junhao Xu
CPC分类号： H01L29/6659 , H01L21/02052 , H01L21/02315 , H01L21/28194 , H01L21/306 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/7833
摘要： An integrated circuit structure includes a semiconductor substrate, and a phonon-screening layer over the semiconductor substrate. Substantially no silicon oxide interfacial layer exists between the semiconductor substrate and the phonon-screening layer. A high-K dielectric layer is located over the phonon-screening layer. A metal gate layer is located over the high-K dielectric layer.
摘要翻译： 集成电路结构包括半导体衬底和半导体衬底上的声子屏蔽层。 在半导体衬底和声子筛选层之间基本上不存在氧化硅界面层。 高K介电层位于声子筛选层上方。 金属栅极层位于高K电介质层的上方。
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