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    Semiconductor Device with a Buried Stressor
    1.
    发明申请
    Semiconductor Device with a Buried Stressor 有权
    具有埋入应力的半导体器件

    公开(公告)号：US20110241084A1

    公开(公告)日：2011-10-06

    申请号：US12750160

    申请日：2010-03-30

    申请人： Zhiqiang Wu ,  Jeffrey Junhao Xu ,  Chih-Hao Chang ,  Wen-Hsing Hsieh

    发明人： Zhiqiang Wu ,  Jeffrey Junhao Xu ,  Chih-Hao Chang ,  Wen-Hsing Hsieh

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848

    摘要： A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.

    摘要翻译： 提供了具有局部应力源的半导体器件，例如PMOS或NMOS器件。 凹槽形成在栅电极的相对侧上。 沿着凹部的底部形成应力诱导区域，在应力诱导区域上形成应力层。 通过具有比应力层更大的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生拉伸应变，并且可以适用于NMOS器件。 通过具有比应力层更小的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生压应变，并且可以适用于PMOS器件。 实施例可以应用于各种类型的基板和半导体器件，例如平面晶体管和finFET。

    Semiconductor device with a buried stressor
    2.
    发明授权
    Semiconductor device with a buried stressor 有权
    具有埋地应力的半导体器件

    公开(公告)号：US08338259B2

    公开(公告)日：2012-12-25

    申请号：US12750160

    申请日：2010-03-30

    申请人： Zhiqiang Wu ,  Jeffrey Junhao Xu ,  Chih-Hao Chang ,  Wen-Hsing Hsieh

    发明人： Zhiqiang Wu ,  Jeffrey Junhao Xu ,  Chih-Hao Chang ,  Wen-Hsing Hsieh

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848

    摘要： A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.

    摘要翻译： 提供了具有局部应力源的半导体器件，例如PMOS或NMOS器件。 凹槽形成在栅电极的相对侧上。 沿着凹部的底部形成应力诱导区域，在应力诱导区域上形成应力层。 通过具有比应力层更大的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生拉伸应变，并且可以适用于NMOS器件。 通过具有比应力层更小的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生压应变，并且可以适用于PMOS器件。 实施例可以应用于各种类型的基板和半导体器件，例如平面晶体管和finFET。

    FinFET method and structure with embedded underlying anti-punch through layer
    3.
    发明授权
    FinFET method and structure with embedded underlying anti-punch through layer 有权
    FinFET方法和结构具有嵌入式底层抗穿透层

    公开(公告)号：US08497171B1

    公开(公告)日：2013-07-30

    申请号：US13541806

    申请日：2012-07-05

    申请人： Wei-Hao Wu ,  Kai-Chieh Yang ,  Wen-Hsing Hsieh ,  Ken-Ichi Goto ,  Zhiqiang Wu

    发明人： Wei-Hao Wu ,  Kai-Chieh Yang ,  Wen-Hsing Hsieh ,  Ken-Ichi Goto ,  Zhiqiang Wu

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823821

    摘要： Methods and structures for forming semiconductor FinFET devices with superior repeatability and reliability include providing APT (anti-punch through) layer accurately formed beneath a semiconductor fins, are provided. Both the n-type and p-type APT layers are formed prior to the formation of the material from which the semiconductor fin is formed. In some embodiments, barrier layers are added between the accurately positioned APT layer and the semiconductor fin. Ion implantation methods and epitaxial growth methods are used to form appropriately doped APT layers in a semiconductor substrate surface. The fin material is formed over the APT layers using epitaxial growth/deposition methods.

    摘要翻译： 用于形成具有优异重复性和可靠性的半导体FinFET器件的方法和结构包括提供准确地形成在半导体鳍片之下的APT（抗穿通）层。 在形成半导体翅片的材料形成之前，形成n型和p型APT层。 在一些实施例中，在精确定位的APT层和半导体鳍片之间添加阻挡层。 使用离子注入方法和外延生长方法在半导体衬底表面中形成适当掺杂的APT层。 使用外延生长/沉积方法在APT层上形成翅片材料。

    Multi-gate semiconductor devices
    5.
    发明授权
    Multi-gate semiconductor devices 有权
    多栅极半导体器件

    公开(公告)号：US08987824B2

    公开(公告)日：2015-03-24

    申请号：US13301873

    申请日：2011-11-22

    申请人： Jon-Hsu Ho ,  Chih-Ching Wang ,  Ching-Fang Huang ,  Wen-Hsing Hsieh ,  Tsung-Hsing Yu ,  Yi-Ming Sheu ,  Chih-Chieh Yeh ,  Ken-Ichi Goto ,  Zhiqiang Wu

    发明人： Jon-Hsu Ho ,  Chih-Ching Wang ,  Ching-Fang Huang ,  Wen-Hsing Hsieh ,  Tsung-Hsing Yu ,  Yi-Ming Sheu ,  Chih-Chieh Yeh ,  Ken-Ichi Goto ,  Zhiqiang Wu

    IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10

    CPC分类号： H01L27/0886 ,  H01L27/0924 ,  H01L29/105 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7851

    摘要： A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

    摘要翻译： 形成包括半导体衬底的多栅极半导体器件。 多栅半导体器件还包括第一晶体管，其包括在半导体衬底之上延伸的第一鳍部。 第一晶体管具有形成在其中的第一沟道区。 第一沟道区域包括以第一掺杂剂类型的第一浓度掺杂的第一沟道区域部分和以第一掺杂剂类型的第二浓度掺杂的第二沟道区域部分。 第二浓度高于第一浓度。 第一晶体管还包括形成在第一沟道区上的第一栅电极层。 第一栅极电极层可以是第二掺杂剂类型。 第一掺杂剂类型可以是N型，第二掺杂剂类型可以是P型。 第二沟道区域部分可以形成在第一沟道区域部分上。