Abstract:
A stability compensation circuit and a DC-DC converter including the same are provided. When an output voltage of the DC-DC converter decreases more than a predetermined value, the stability compensation circuit quickly charges an integral capacitor by using an additional converter or by reducing an effective resistance of a charging circuit which charges the capacitor. Since an output voltage of an integrator in the stability compensation circuit is enabled to quickly reach a control voltage, the instant decrease of the output voltage of the DC-DC converter can be quickly compensated for.
Abstract:
A power converter includes a power switch adapted to receive an input power from an external power source and to generate an output power, and an adaptive oscillator adapted to output an adaptive minimum-on signal of the power switch in response to a change in measured magnitude of at least one of the input power and the output power.
Abstract:
A maximum voltage source selector adapted for use in a semiconductor device operative in a disable state or an enable state is disclosed. The maximum voltage source selector includes an output unit having an output node providing a maximum voltage selected from a first input voltage and a second input voltage. First and second gate transistors are commonly coupled to the output node and are respectively configured to select and provide the greater of the first and second input voltages to the output node in response to first and second selection signals without regard to whether the semiconductor device is in the disable state or the enable state. A selection unit generates the first and second selection signals in response to the first and second input voltages.
Abstract:
Provided are a circuit for and a method of eliminating pop noise in a digital audio amplifier using dual power supply, which are simple, drop in price, and can be readily implemented in a semiconductor chip. According to an existing technique, pop noise is eliminated using a relay. However, in the present circuit and method, pop noise is eliminated using the small number of discrete electronic devices. The circuit for eliminating pop noise controls a voltage at a gate of a power switch, i.e., a power MOS transistor, when power supply voltages are applied and the application of power supply voltages is stopped.
Abstract:
Disclosed are flat/vertical type vacuum field transistor (VFT) structures, which adopt a MOSFET-like flat or vertical structure so as to increase the degree of integration and can be operated at low operation voltages at high speeds. The flat type comprises a source and a drain, made of conductors, which stand at a predetermined distance apart on a thin channel insulator with a vacuum channel therebetween; a gate, made of a conductor, which is formed with a width below the source and the drain, the channel insulator functioning to insulate the gate from the source and the drain; and an insulating body, which serves as a base for propping up the channel insulator and the gate. The vertical type comprises a conductive, continuous circumferential source with a void center, formed on a channel insulator; a conductive gate formed below the channel insulator, extending across the source; an insulating body for serving as a base to support the gate and the channel insulator; an insulating walls which stand over the source, forming a closed vacuum channel; and a drain formed over the vacuum channel. In both types, proper bias voltages are applied among the gate, the source and the drain to enable electrons to be field emitted from the source through the vacuum channel to the drain.
Abstract:
A reset control apparatus may include a first reference generator adapted to output a first reference value in response to an enable signal from an external power source, a second reference generator adapted to receive the first reference value and to output a second reference value, and a set signal generator adapted to output a set signal when the second reference value exceeds a predetermined value.
Abstract:
A maximum voltage source selector adapted for use in a semiconductor device operative in a disable state or an enable state is disclosed. The maximum voltage source selector includes an output unit having an output node providing a maximum voltage selected from a first input voltage and a second input voltage. First and second gate transistors are commonly coupled to the output node and are respectively configured to select and provide the greater of the first and second input voltages to the output node in response to first and second selection signals without regard to whether the semiconductor device is in the disable state or the enable state. A selection unit generates the first and second selection signals in response to the first and second input voltages.
Abstract:
A reset control apparatus may include a first reference generator adapted to output a first reference value in response to an enable signal from an external power source, a second reference generator adapted to receive the first reference value and to output a second reference value, and a set signal generator adapted to output a set signal when the second reference value exceeds a predetermined value.
Abstract:
This disclosure provides a method and apparatus for reducing an inrush current inflowing from an external power source during an initial transient state. The method may include generating a first signal based on a level of internal voltage. The first signal may linearly increase or decrease, wherein the slope of the first signal may be fixed. The method may further include comparing the first signal with the reference voltage, and controlling an overcurrent prevention function based on the comparison results. An inrush current reducing device may include a reference voltage generating unit configured to compare a first signal and the reference voltage to control an overcurrent sensing gain, a gain unit configured to compare a first signal and the reference voltage to control an overcurrent sensing gain, and an overcurrent prevention signal generating unit configured to control an overcurrent prevention function based on the comparison results.
Abstract:
A negative supply voltage generating circuit includes a pulse generating circuit and a charge pump. The pulse generating circuit generates a first pulse signal and a second pulse signal in response to a clock signal. The first and second pulse signals have pulse widths different from each other. The charge pump generates a negative supply voltage by performing a charge pumping operation in response to the first and second pulse signals, and has a time interval between a switch-on time duration for charging a flying capacitor and a switch-on time duration for transmitting charges to an output capacitor.