公开(公告)号：US06790756B2

公开(公告)日：2004-09-14

申请号：US10385954

申请日：2003-03-11

申请人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So Wein Kuo

发明人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So Wein Kuo

IPC分类号： H01L213205

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

摘要翻译： 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US6140693A

公开(公告)日：2000-10-31

申请号：US345356

申请日：1999-07-01

申请人： Jiue Wen Weng ,  Ruey-Yun Shiue

发明人： Jiue Wen Weng ,  Ruey-Yun Shiue

IPC分类号： H01L21/02 ,  H01L29/00

CPC分类号： H01L28/40

摘要： A method for making metal capacitors for deep submicrometer processes for integrated circuits is described. The method provides metal capacitors with high capacitance per unit area, low voltage coefficients, and excellent capacitance distribution (uniformity) across the substrate. The method involves depositing a first insulating layer on a substrate having completed semiconductor devices. A first metal layer is deposited and patterned to form bottom electrodes and interconnecting metal lines. A thin capacitor dielectric layer is deposited, and a thin second metal or TiN layer is deposited and patterned to form the top electrodes. A thick second insulating layer is deposited and planarized, and an array of via holes are etched to the top electrodes to provide for low-resistance contacts and via holes for the interconnecting metal lines. A third conducting metal layer is deposited over the second insulating layer and in the via holes, and is patterned to form a thick metal plate over the capacitors to provide low-resistance contacts to the capacitors and concurrently to form the next level of metal interconnections.

摘要翻译： 描述了一种制造用于集成电路深亚微米工艺的金属电容器的方法。 该方法提供金属电容器，每单位面积具有高电容，低电压系数，以及优异的电容分布（均匀性）。 该方法包括在具有完成的半导体器件的衬底上沉积第一绝缘层。 沉积和图案化第一金属层以形成底部电极并互连金属线。 沉积薄的电容器电介质层，并且沉积和图案化薄的第二金属或TiN层以形成顶部电极。 沉积并平坦化厚的第二绝缘层，并且将通孔阵列蚀刻到顶部电极以提供用于互连金属线的低电阻触点和通孔。 第三导电金属层沉积在第二绝缘层上和通孔中，并被图案化以在电容器上形成厚的金属板，以向电容器提供低电阻触点并同时形成下一级金属互连。

公开(公告)号：US5631188A

公开(公告)日：1997-05-20

申请号：US578924

申请日：1995-12-27

申请人： Ming-Hsung Chang ,  Jiue-Wen Weng

发明人： Ming-Hsung Chang ,  Jiue-Wen Weng

IPC分类号： H01L21/02 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L28/40

摘要： A method for forming a low voltage coefficient capacitor within an integrated circuit. Formed upon a semiconductor substrate is a first polysilicon layer. Formed directly upon the first polysilicon layer is an Inter Polysilicon Dielectric (IPD) layer. Formed directly upon the Inter Polysilicon Dielectric (IPD) layer is a second polysilicon layer. The first polysilicon layer and the second polysilicon layer each have a resistivity no greater than about 40 ohms per square. Formed directly upon the second polysilicon layer is an amorphous silicon layer. Formed directly upon the amorphous silicon layer is a metal layer which is capable of forming a metal silicide with the amorphous silicon layer. The thickness of the metal layer and the thickness of the amorphous silicon layer are chosen to form a stoichiometric metal silicide with minimal consumption of the polysilicon layer. Finally, the semiconductor substrate is annealed to form a metal silicide layer from the amorphous silicon layer and the metal layer.

摘要翻译： 一种用于在集成电路内形成低电压系数电容器的方法。 形成在半导体衬底上的是第一多晶硅层。 形成在第一多晶硅层上的是多晶硅介电层（IPD）层。 在多晶硅介质（IPD）层上直接形成第二多晶硅层。 第一多晶硅层和第二多晶硅层各自具有不大于约40欧姆/平方的电阻率。 直接形成在第二多晶硅层上的是非晶硅层。 直接形成在非晶硅层上的是能够与非晶硅层形成金属硅化物的金属层。 选择金属层的厚度和非晶硅层的厚度以形成化学计量的金属硅化物，同时具有最小的多晶硅层消耗。 最后，半导体衬底被退火以从非晶硅层和金属层形成金属硅化物层。

公开(公告)号：US06583017B2

公开(公告)日：2003-06-24

申请号：US09927072

申请日：2001-08-10

申请人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

发明人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

摘要翻译： 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US06211069B1

公开(公告)日：2001-04-03

申请号：US09312601

申请日：1999-05-17

申请人： Chu-Wei Hu ,  Jiue Wen Weng ,  Ruey Yun Shiue

发明人： Chu-Wei Hu ,  Jiue Wen Weng ,  Ruey Yun Shiue

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/76813

摘要： A process for forming a dual damascene opening, in a composite insulator layer, comprised of an overlying, wide diameter opening, used to accommodate a metal interconnect structure, and comprised of an underlying, narrow diameter opening, used to accommodate a metal via structure, has been developed. The process features the use of conventional photolithographic and anisotropic dry etching procedures, used to create an initial dual damascene opening, in the composite insulator layer. The subsequent formation of insulator spacers, on the vertical sides of the initial dual damascene opening, however, results in a final dual damascene opening, featuring a diameter smaller than the diameter displayed with the initial dual damascene opening.

摘要翻译： 一种在复合绝缘体层中形成双镶嵌开口的方法，包括用于容纳金属互连结构的上覆的宽直径开口，并且包括用于容纳金属通孔结构的下面的窄直径的开口， 已经开发。 该方法的特征在于在复合绝缘体层中使用常规光刻和各向异性干蚀刻方法，用于产生初始的双镶嵌开口。 然而，在初始双镶嵌开口的垂直侧面上随后形成绝缘体间隔件，导致最终的双镶嵌开口，其直径小于初始双镶嵌开口所显示的直径。

公开(公告)号：US5946567A

公开(公告)日：1999-08-31

申请号：US44761

申请日：1998-03-20

申请人： Jiue Wen Weng ,  Ruey-Yun Shiue

发明人： Jiue Wen Weng ,  Ruey-Yun Shiue

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L28/40

摘要： A method for making metal capacitors for deep submicrometer processes for integrated circuits is described. The method provides metal capacitors with high capacitance per unit area, low voltage coefficients, and excellent capacitance distribution (uniformity) across the substrate. The method involves depositing a first insulating layer on a substrate having completed semiconductor devices. A first metal layer is deposited and patterned to form bottom electrodes and interconnecting metal lines. A thin capacitor dielectric layer is deposited, and a thin second metal or TiN layer is deposited and patterned to form the top electrodes. A thick second insulating layer is deposited and planarized, and an array of via holes are etched to the top electrodes to provide for low-resistance contacts and via holes for the interconnecting metal lines. A third conducting metal layer is deposited over the second insulating layer and in the via holes, and is patterned to form a thick metal plate over the capacitors to provide low-resistance contacts to the capacitors and concurrently to form the next level of metal interconnections.

公开(公告)号：US06287926B1

公开(公告)日：2001-09-11

申请号：US09253297

申请日：1999-02-19

申请人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

发明人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

摘要翻译： 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。