利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

29 条记录 (耗时 0.032 秒)

    STRUCTURE AND METHOD OF MAKING A FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRICALLY STRESSED CHANNEL REGION
    1.
    发明申请
    STRUCTURE AND METHOD OF MAKING A FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRICALLY STRESSED CHANNEL REGION 有权
    制造具有非对称应力通道区域的场效应晶体管的结构和方法

    公开(公告)号：US20060255415A1

    公开(公告)日：2006-11-16

    申请号：US10908448

    申请日：2005-05-12

    申请人： Gregory Freeman ,  Anil Chinthakindi ,  David Greenberg ,  Basanth Jagannathan ,  Marwan Khater ,  John Pekarik ,  Xudong Wang

    发明人： Gregory Freeman ,  Anil Chinthakindi ,  David Greenberg ,  Basanth Jagannathan ,  Marwan Khater ,  John Pekarik ,  Xudong Wang

    IPC分类号： H01L29/76

    CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7843

    摘要： A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.

    摘要翻译： 提供一种场效应晶体管，其包括其中设置有源极区，沟道区和漏极区的邻接单晶半导体区。 沟道区域具有与源极区域共同的边缘作为源极边缘，并且沟道区域还具有与作为漏极边缘的漏极区域共同的边缘。 栅极导体覆盖沟道区域。 场效应晶体管还包括将源极边缘和漏极边缘的另一个施加不大于第二幅度的应力的第一幅度的应力仅施加到源极边缘和漏极边缘中的一个的结构， 其中所述第二幅度具有从零到所述第一幅度的大约一半的值。 在特定实施例中，将应力以第一幅度施加到源极边缘，同时零或较小幅度应力施加到漏极边缘。 在另一个实施例中，将应力以第一幅度施加到漏极边缘，同时将零或较小的幅度应力施加到漏极边缘。

    Field effect transistor having an asymmetrically stressed channel region
    2.
    发明授权
    Field effect transistor having an asymmetrically stressed channel region 有权
    具有不对称应力通道区域的场效应晶体管

    公开(公告)号：US07355221B2

    公开(公告)日：2008-04-08

    申请号：US10908448

    申请日：2005-05-12

    申请人： Gregory G. Freeman ,  Anil K. Chinthakindi ,  David R. Greenberg ,  Basanth Jagannathan ,  Marwan H. Khater ,  John Pekarik ,  Xudong Wang

    发明人： Gregory G. Freeman ,  Anil K. Chinthakindi ,  David R. Greenberg ,  Basanth Jagannathan ,  Marwan H. Khater ,  John Pekarik ,  Xudong Wang

    IPC分类号： H01L29/76

    CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7843

    摘要： A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.

    摘要翻译： 提供一种场效应晶体管，其包括其中设置有源极区，沟道区和漏极区的邻接单晶半导体区。 沟道区域具有与源极区域共同的边缘作为源极边缘，并且沟道区域还具有与作为漏极边缘的漏极区域共同的边缘。 栅极导体覆盖沟道区域。 场效应晶体管还包括将源极边缘和漏极边缘的另一个施加不大于第二幅度的应力的第一幅度的应力仅施加到源极边缘和漏极边缘中的一个的结构， 其中所述第二幅度具有从零到所述第一幅度的大约一半的值。 在特定实施例中，将应力以第一幅度施加到源极边缘，同时零或较小幅度应力施加到漏极边缘。 在另一个实施例中，将应力以第一幅度施加到漏极边缘，同时将零或较小的幅度应力施加到漏极边缘。

    STRUCTURE AND LAYOUT OF A FET PRIME CELL
    3.
    发明申请
    STRUCTURE AND LAYOUT OF A FET PRIME CELL 审中-公开
    FET母细胞的结构和布局

    公开(公告)号：US20060071304A1

    公开(公告)日：2006-04-06

    申请号：US10711640

    申请日：2004-09-29

    申请人： Basanth Jagannathan ,  John Pekarik ,  Christopher Schnabel

    发明人： Basanth Jagannathan ,  John Pekarik ,  Christopher Schnabel

    IPC分类号： H01L23/552

    CPC分类号： H01L29/78 ,  H01L23/4824 ,  H01L29/1087

    摘要： A structure, apparatus and method for a FET prime cell surrounded by a conductor is provided. The surrounding conductor includes a substrate contact arranged proximate a source of the FET. The surrounding conductor may be a ring substrate contact arranged within the substrate of the FET in electrical communication with elongated sources of the FET. No external contacts are needed to the ring substrate contact because no current flows therethrough while the ring substrate contact may act as a collection source for noise such as stray currents.

    摘要翻译： 提供了由导体包围的FET素电池的结构，装置和方法。 周围导体包括靠近FET的源极布置的衬底接触。 周围导体可以是布置在FET的衬底内的环形衬底接触，与FET的细长源电连通。 由于没有电流流过其中，环形基板接触可能作为用于诸如杂散电流的噪声的收集源，因此环形基板接触不需要外部接触。

    System and method for de-embedding a device under test employing a parametrized netlist
    9.
    发明授权
    System and method for de-embedding a device under test employing a parametrized netlist 失效
    使用参数化网表解嵌入被测设备的系统和方法

    公开(公告)号：US07741857B2

    公开(公告)日：2010-06-22

    申请号：US12043169

    申请日：2008-03-06

    申请人： Basanth Jagannathan ,  Zhenrong Jin ,  Hongmei Li

    发明人： Basanth Jagannathan ,  Zhenrong Jin ,  Hongmei Li

    IPC分类号： G01R35/00 ,  G01D18/00 ,  G01P21/00

    CPC分类号： G01R27/32 ,  G01R35/00

    摘要： S-parameter data is measured on an embedded device test structure, an open dummy, and a short dummy. A 4-port network of the pad set parasitics of the embedded device test structure is modeled by a parameterized netlist containing a lumped element network having at least one parameterized lumped element. The S-parameter data across a range of measurement frequencies is fitted with the parameterized netlist employing the at least one parameterized lumped element as at least one fitting parameter for the S-parameter data. Thus, the fitting method is a multi-frequency fitting for the at least one parameterized lumped element. A 4-port Y-parameter (admittance parameter) is obtained from the fitted parameterized netlist. The Y-parameter of the device under test is obtained from the measured admittance of the embedded device test structure and the calculated 4-port Y parameter.

    摘要翻译： S参数数据是在嵌入式设备测试结构上测量的，一个开放虚拟的和一个短虚拟的。 嵌入式设备测试结构的焊盘组寄生效应的4端口网络由包含具有至少一个参数化集总元件的集总元件网络的参数化网表建模。 跨越测量频率范围的S参数数据与采用至少一个参数化集总元件的参数化网表相配合，作为S参数数据的至少一个拟合参数。 因此，拟合方法是用于至少一个参数化的集总元件的多频率拟合。 从拟合的参数化网表获得4端口Y参数（导纳参数）。 被测器件的Y参数是从嵌入式器件测试结构的测量导纳和计算的4端口Y参数获得的。