公开(公告)号：US08228715B2

公开(公告)日：2012-07-24

申请号：US12789838

申请日：2010-05-28

Applicant: Thomas Andre ,  Saied Tehrani ,  Jon Slaughter ,  Nicholas Rizzo

Inventor： Thomas Andre ,  Saied Tehrani ,  Jon Slaughter ,  Nicholas Rizzo

IPC: G11C11/00 ,  G11C11/14

CPC classification number: G11C11/1657 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: An apparatus and method of programming a spin-torque magnetoresistive memory array includes a metal reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state by generating a magnetic field when an electrical current flows through it. A spin torque transfer current is then applied to selected ones of the magnetoresistive bits to switch the selected bit to a programmed state. In another mode of operation, a resistance of the plurality of bits is sensed prior to generating the magnetic field. The resistance is again sensed after the magnetic field is generated and the data represented by the initial state of each bit is determined from the resistance change. A spin torque transfer current is then applied only to those magnetoresistive bits having a resistance different from prior to the magnetic field being applied.

Abstract translation: 编程自旋转矩磁阻存储器阵列的装置和方法包括位于多个磁阻位中的每一个附近的金属复位线，并且被配置为通过在电流下产生磁场将多个磁阻存储元件设置为已知状态 流过它 然后将自旋转矩传递电流施加到选定的磁阻位，以将所选位切换到编程状态。 在另一种操作模式中，在产生磁场之前感测到多个位的电阻。 在产生磁场之后再次感测电阻，并且根据电阻变化确定由每个位的初始状态表示的数据。 然后，自旋转矩传递电流仅施加于具有与施加磁场之前不同的电阻的那些磁阻位。

公开(公告)号：US20120081950A1

公开(公告)日：2012-04-05

申请号：US12895057

申请日：2010-09-30

Applicant: Jon SLAUGHTER

Inventor： Jon SLAUGHTER

IPC: G11C11/00

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: An apparatus and method of programming a spin-torque magnetoresistive memory array includes a conductive reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state having magnetization perpendicular to the film plane of the magnetoresistive bits by generating a magnetic field when an electrical current flows therethrough. The conductive reset line is positioned such that the magnetic field is applied with a predominant component perpendicular to the film plane when an electrical current of predetermined magnitude, duration, and direction flows through the first conductive reset line. Another conductive reset line may be positioned wherein the magnetic field is created between the two conductive reset lines. A permeable ferromagnetic material may be positioned around a portion of the conductive reset line or lines to focus the magnetic field in the desired direction by positioning edges of permeable ferromagnetic material on opposed sides of the film plane. A spin torque transfer current is applied to selected ones of the magnetoresistive bits to switch the selected bit to a programmed state.

Abstract translation: 编程自旋扭矩磁阻存储器阵列的装置和方法包括位于多个磁阻位中的每一个附近的导电复位线，并且被配置为将多个磁阻存储元件设置为具有垂直于 当电流流过其中时，产生磁场。 定位导电复位线，使得当预定幅度，持续时间和方向的电流流过第一导电复位线时，磁场被施加垂直于膜平面的主要分量。 可以定位另一个导电复位线，其中在两个导电复位线之间产生磁场。 可渗透的铁磁材料可以围绕导电复位线或线的一部分定位，以通过将可渗透铁磁材料的边缘定位在膜平面的相对侧上来将磁场聚焦在期望的方向上。 自旋扭矩传递电流被施加到所选磁阻位中，以将所选位切换到编程状态。

公开(公告)号：US20110244599A1

公开(公告)日：2011-10-06

申请号：US12751927

申请日：2010-03-31

Applicant: Renu WHIG ,  Phillip MATHER ,  Kenneth SMITH ,  Sanjeev AGGARWAL ,  Jon SLAUGHTER ,  Nicholas RIZZO

Inventor： Renu WHIG ,  Phillip MATHER ,  Kenneth SMITH ,  Sanjeev AGGARWAL ,  Jon SLAUGHTER ,  Nicholas RIZZO

IPC: H01L43/12 ,  H01L21/768

CPC classification number: H01L43/12 ,  B82Y25/00 ,  G01R33/0052 ,  G01R33/09 ,  G01R33/093 ,  G01R33/098 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

Abstract translation: 半导体工艺集成了三个桥接电路，每个电路包括在单个芯片上作为惠斯登电桥耦合的磁阻传感器，以在三个正交方向上感测磁场。 该过程包括形成磁阻传感器的各种沉积和蚀刻步骤以及在三个桥接电路中的一个上的多个通量引导器，用于将“Z”轴磁场传送到在XY平面中定向的传感器上。

公开(公告)号：US20050047198A1

公开(公告)日：2005-03-03

申请号：US10647976

申请日：2003-08-25

Applicant: Bradley Engel ,  Eric Salter ,  Jon Slaughter

Inventor： Bradley Engel ,  Eric Salter ,  Jon Slaughter

IPC: G11C11/15 ,  G11C11/16 ,  G11C11/56 ,  G11C11/00

CPC classification number: G11C11/16 ,  G11C11/5607

Abstract: A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device (12) having two bits (18) and (20) sandwiched between a word line (14) and a digit line (16) so that current waveforms (104) and (106) can be applied to the word and digit lines at various times to cause a magnetic field flux HW and HD to rotate the effective magnetic moment vectors (86) and (94) of the device (12) by approximately 180°. Each bit includes N ferromagnetic layers (32) and (34, 42) and (44, 60) and (62, 72 and 74) that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the bit. One or both bits may be programmed by adjusting the current in the word and/or digit lines.

Abstract translation: 一种用于切换可扩展磁阻存储单元的方法，包括以下步骤：提供具有夹在字线（14）和数字线（16）之间的两个位（18）和（20）的磁阻存储器件（12），使得电流波形 （104）和（106）可以在不同时间施加到字和数字线，以使磁场通量HW和HD将装置（12）的有效磁矩矢量（86）和（94）旋转大约 180°。 每个位包括反铁磁耦合的N个铁磁层（32）和（34,42）和（44,60）和（62,72和74）。 可以调节N以改变位的磁开关量。 可以通过调整字和/或数字线中的电流来编程一个或两个位。

公开(公告)号：US20050045929A1

公开(公告)日：2005-03-03

申请号：US10648466

申请日：2003-08-25

Applicant: Jason Janesky ,  Bradley Engel ,  Jon Slaughter

Inventor： Jason Janesky ,  Bradley Engel ,  Jon Slaughter

IPC: G11C11/15 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30 ,  H01L29/76 ,  H01L31/119 ,  H01L43/08

CPC classification number: H01F10/3272 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  H01F10/3254 ,  H01F41/302 ,  H01L43/08

Abstract: An array of multi-state, multi-layer magnetic memory devices (10) wherein each memory device comprises a nonmagnetic spacer region (22) and a free magnetic region (24) positioned adjacent to a surface of the nonmagnetic spacer region, the free magnetic region including a plurality of magnetic layers (36,34,38), wherein the magnetic layer (36) in the plurality of magnetic layers positioned adjacent to the surface of the nonmagnetic spacer region has a thickness substantially greater than a thickness of each of the magnetic layers (34,38) subsequently grown thereon wherein the thickness is chosen to improve the magnetic switching variation so that the magnetic switching field for each memory device in the array of memory devices is more uniform.

Abstract translation: 一种多状态多层磁存储器件阵列，其中每个存储器件包括非磁性间隔区域（22）和邻近非磁性间隔区域表面定位的自由磁区域（24），所述自由磁性区域 区域，其包括多个磁性层（36,34,38），其中位于所述非磁性间隔区域的表面附近的所述多个磁性层中的所述磁性层（36）的厚度基本上大于所述非磁性间隔区域的厚度 随后在其上生长的磁性层（34,38），其中选择厚度以改善磁切换变化，使得存储器件阵列中的每个存储器件的磁切换场更均匀。

公开(公告)号：US20150023093A1

公开(公告)日：2015-01-22

申请号：US14313824

申请日：2014-06-24

Applicant: Michael Schneider ,  Dimitri Houssameddine ,  Jon Slaughter

Inventor： Michael Schneider ,  Dimitri Houssameddine ,  Jon Slaughter

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1673

Abstract: Circuitry and a method provide an increased tunnel barrier endurance (lifetime) previously shortened by dielectric breakdown by providing a pulse of opposite polarity associated with a write pulse. The pulse of opposite polarity may comprise equal or less width and amplitude than that of the write pulse, may be applied with each write pulse or a series of write pulses, and may be applied prior to or subsequent to the write pulse.

Abstract translation: 电路和方法通过提供与写入脉冲相关的相反极性的脉冲，提供先前通过电介质击穿缩短的隧道势垒耐力（寿命）。 相反极性的脉冲可以包括与写入脉冲相等或更小的宽度和幅度，可以用每个写入脉冲或一系列写入脉冲施加，并且可以在写入脉冲之前或之后施加。

公开(公告)号：US20130106410A1

公开(公告)日：2013-05-02

申请号：US13286026

申请日：2011-10-31

Applicant: Lianjun Liu ,  Philip Mather ,  Jon Slaughter

Inventor： Lianjun Liu ,  Philip Mather ,  Jon Slaughter

IPC: G01R33/02

CPC classification number: G01R33/0029 ,  G01R33/0041 ,  G01R33/04 ,  G01R33/098

Abstract: A magnitude and direction of at least one of a reset current and a second stabilization current (that produces a reset field and a second stabilization field, respectively) is determined that, when applied to an array of magnetic sense elements, minimizes the total required stabilization field and reset field during the operation of the magnetic sensor and the measurement of the external field. Therefore, the low field sensor operates optimally (with the highest sensitivity and the lowest power consumption) around the fixed external field operating point. The fixed external field is created by other components in the sensor device housing (such as speaker magnets) which have a high but static field with respect to the low (earth's) magnetic field that describes orientation information.

公开(公告)号：US08390283B2

公开(公告)日：2013-03-05

申请号：US12567496

申请日：2009-09-25

Applicant: Phillip Mather ,  Jon Slaughter ,  Nicholas Rizzo

Inventor： Phillip Mather ,  Jon Slaughter ,  Nicholas Rizzo

IPC: G01R33/02 ,  G01R33/00

CPC classification number: H01L27/22 ,  B82Y25/00 ,  G01R33/093 ,  H01L43/08

Abstract: Three bridge circuits (101, 111, 121), each include magnetoresistive sensors coupled as a Wheatstone bridge (100) to sense a magnetic field (160) in three orthogonal directions (110, 120, 130) that are set with a single pinning material deposition and bulk wafer setting procedure. One of the three bridge circuits (121) includes a first magnetoresistive sensor (141) comprising a first sensing element (122) disposed on a pinned layer (126), the first sensing element (122) having first and second edges and first and second sides, and a first flux guide (132) disposed non-parallel to the first side of the substrate and having an end that is proximate to the first edge and on the first side of the first sensing element (122). An optional second flux guide (136) may be disposed non-parallel to the first side of the substrate and having an end that is proximate to the second edge and the second side of the first sensing element (122).

Abstract translation: 三桥电路（101,111,121）各自包括耦合为惠斯通电桥（100）的磁阻传感器，用于在三个垂直方向（110,120,130）上感测磁场（160），所述三个正交方向（110,120,130）设置有单个钉扎材料 沉积和体晶片设置程序。 三个桥接电路（121）中的一个包括第一磁阻传感器（141），其包括设置在被钉扎层（126）上的第一感测元件（122），第一感测元件（122）具有第一和第二边缘以及第一和第二 侧面，以及第一磁通引导件（132），其布置成不平行于衬底的第一侧面并且具有靠近第一边缘并且在第一感测元件（122）的第一侧上的端部。 可选的第二磁通引导件136可以布置成不平行于衬底的第一侧并且具有靠近第一感测元件（122）的第二边缘和第二侧的端部。

公开(公告)号：US20120313191A1

公开(公告)日：2012-12-13

申请号：US13158171

申请日：2011-06-10

Applicant: Renu WHIG ,  Jon SLAUGHTER ,  Nicholas RIZZO ,  Jijun SUN ,  Frederick MANCOFF ,  Dimitri HOUSSAMEDDINE

Inventor： Renu WHIG ,  Jon SLAUGHTER ,  Nicholas RIZZO ,  Jijun SUN ,  Frederick MANCOFF ,  Dimitri HOUSSAMEDDINE

IPC: H01L29/82 ,  H01L21/02

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A spin-torque magnetoresistive memory element has a high magnetoresistance and low current density. A free magnetic, layer is positioned between first and second spin polarizers. A first tunnel barrier is positioned between the first spin polarizer and the free magnetic layer and a second tunnel barrier is positioned between the second spin polarizer and the free magnetic layer. The magnetoresistance ratio of the second tunnel barrier has a value greater than double the magnetoresistance ratio of the first tunnel barrier.

Abstract translation: 自旋转矩磁阻存储元件具有高磁阻和低电流密度。 自由磁性层位于第一和第二自旋偏振器之间。 第一隧道势垒位于第一自旋偏振器和自由磁性层之间，第二隧道势垒位于第二自旋偏振器和自由磁性层之间。 第二隧道势垒的磁阻比具有大于第一隧道势垒的磁阻比的两倍的值。

公开(公告)号：US20110147867A1

公开(公告)日：2011-06-23

申请号：US12645749

申请日：2009-12-23

Applicant: Jon Slaughter ,  Phillip Mather

Inventor： Jon Slaughter ,  Phillip Mather

IPC: H01L27/20 ,  H01L21/98 ,  H01L21/50

CPC classification number: H01L27/22 ,  B82Y25/00 ,  G01R33/093 ,  G01R33/098 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14

Abstract: A method of mounting a first integrated circuit (102, 500, 704) on one of a circuit board (300, 700) or a second integrated circuit (706), the first integrated circuit (102, 500, 704) formed over a substrate (104) and having a surface (119) opposed to the substrate (104) and a side (122, 530, 930) substantially orthogonal to the surface (119), and including a conductive element (116, 117, 118, 522, 524, 526, 528, 528′, 528″) coupled to circuitry (102, 500, 704) and formed within a dielectric material (120, 518), the one of the circuit board (300, 700) or the second integrated circuit (706) including a contact point (304, 306, 314), the method including singulating (1104) the first integrated circuit (102, 500, 704) to expose the conductive element (116, 117, 118, 522, 524, 526, 528, 528′, 528″) on the side (222, 630, 1030), and mounting (1108) the first integrated circuit (102, 500, 704) on the one of a circuit board (300, 700) or a second integrated circuit (706) by aligning the conductive element (116, 117, 118, 522, 524, 526, 528, 528′, 528″) exposed on the side (222, 630, 1030) to make electrical contact with the contact point (304, 306, 314).

Abstract translation: 一种将第一集成电路（102,500,704）安装在电路板（300,700）或第二集成电路（706）之一上的方法，所述第一集成电路（102,500,704）形成在衬底 （104），并且具有与所述基板（104）相对的表面（119）和与所述表面（119）基本正交的侧面（122,530,930），并且包括导电元件（116,117,118,522） 耦合到电路（102,500,704）并且形成在介电材料（120,518）内的电路板（300,700）或第二集成电路（120,518）中的一个 （706）包括接触点（304,306,314），所述方法包括对所述第一集成电路（102,500,604）进行单独（1104）以暴露所述导电元件（116,117，118,522,524,526） ，528,582'，528“），并且将第一集成电路（102,500,604）安装（1108）在电路板（300,700）或 第二集成电路（706） 导电元件（116,117,118,522,524,526,528,528'，528“）暴露在侧面（222,630,1030）上以与接触点（304,306,314）电接触， 。