公开(公告)号：US09019013B2

公开(公告)日：2015-04-28

申请号：US14008573

申请日：2011-10-13

申请人： Jong Hoon Park ,  Chang Kun Park

发明人： Jong Hoon Park ,  Chang Kun Park

IPC分类号： H03F3/45 ,  H03F3/21

CPC分类号： H03F3/45179 ,  H03F3/21 ,  H03F3/45183 ,  H03F2203/45034 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45481 ,  H03F2203/45638

摘要： Provided is a power amplifier which includes: a first transistor and a second transistor each having a first end connected to a first power source supplying a first voltage and to which signals having a same size but opposite polarities are input; a third transistor and a fourth transistor having first ends respectively connected to the first ends of the first transistor and the second transistor; and a fifth transistor having a first end connected to second ends of the third and fourth transistors and controlling oscillation of the third or fourth transistor.

摘要翻译： 提供了一种功率放大器，其包括：第一晶体管和第二晶体管，每个具有连接到提供第一电压的第一电源的第一端，并且输入具有相同尺寸但相反极性的信号; 第三晶体管和第四晶体管，其第一端分别连接到第一晶体管和第二晶体管的第一端; 以及第五晶体管，其第一端连接到第三和第四晶体管的第二端并控制第三或第四晶体管的振荡。

公开(公告)号：US08760257B2

公开(公告)日：2014-06-24

申请号：US13880163

申请日：2011-09-07

申请人： Jong Hoon Park ,  Chang Kun Park

发明人： Jong Hoon Park ,  Chang Kun Park

IPC分类号： H01F5/00

CPC分类号： H01F27/2852 ,  H01F19/04 ,  H01P5/04

摘要： Provided is a transmission line transformer, and more particularly, a transmission line transformer capable of decreasing a power loss caused by a parasitic resistance component of the transmission line transformer and improving a coupling factor by forming a primary transmission line and a secondary transmission line parallel to each other on an integrated circuit (IC) by using a highest layer metal line, and forming a lower layer metal line immediately below the highest layer metal line in addition to the highest layer metal line in a region where the primary transmission line and the secondary transmission line face each other, while forming the transmission line transformer used in a high frequency circuit via a semiconductor process.

摘要翻译： 提供了一种传输线变压器，更具体地，涉及一种传输线变压器，其能够降低由传输线变压器的寄生电阻分量引起的功率损耗，并且通过形成与第一传输线平行的第一传输线和二次传输线来提高耦合系数 通过使用最高层金属线在集成电路（IC）上彼此相互连接，并且在最高层金属线的正下方形成下层金属线，除了在主传输线和次级侧的区域中的最高层金属线之外 传输线彼此面对，同时通过半导体工艺形成用于高频电路的传输线变压器。

公开(公告)号：US20140017163A1

公开(公告)日：2014-01-16

申请号：US13546833

申请日：2012-07-11

申请人： Kug Sun Hong ,  Seong Sik Shin ,  Jae Ho Suk ,  Sang Baek Park ,  Jong Hoon Park ,  In Sun Cho ,  Dong Wook Kim

发明人： Kug Sun Hong ,  Seong Sik Shin ,  Jae Ho Suk ,  Sang Baek Park ,  Jong Hoon Park ,  In Sun Cho ,  Dong Wook Kim

IPC分类号： C01F11/02

CPC分类号： C01G19/00 ,  C01P2002/72 ,  C01P2004/50 ,  C01P2004/61 ,  C01P2004/64 ,  H01G9/2027 ,  H01L21/02565 ,  H01L21/02628 ,  Y02E10/542 ,  Y02P70/521

摘要： Disclosed herein is a method of preparing a ternary oxide semiconductor compound, including the steps of: dissolving an inorganic salt source including Sn and an inorganic salt source including at least one selected from the alkali earth metal group consisting of Ba, Sr and Ca in a mixed solvent of water and hydrogen peroxide to form a mixed solution; precipitating the mixed solution by changing the PH thereof to obtain a precipitate and then aging the precipitate; and drying and then annealing the aged precipitate to prepare MSnO3 powder (here, M includes at least one selected from the group consisting of Ba, Sr and Ca). The method is advantageous in that a nanosized ternary oxide semiconductor compound having a uniform particle size distribution can be prepared.

摘要翻译： 本文公开了一种三元氧化物半导体化合物的制备方法，包括以下步骤：将包含Sn的无机盐源和包含选自由Ba，Sr和Ca组成的碱土金属组中的至少一种的无机盐源溶解在 水和过氧化氢的混合溶剂形成混合溶液; 通过改变其PH而使混合溶液沉淀得到沉淀物，然后使沉淀物老化; 然后干燥然后使老化的沉淀物退火以制备MSnO 3粉末（这里，M包括选自Ba，Sr和Ca中的至少一种）。 该方法的优点在于可以制备具有均匀粒度分布的纳米尺寸三元氧化物半导体化合物。

公开(公告)号：US20110220727A1

公开(公告)日：2011-09-15

申请号：US13129653

申请日：2008-11-19

申请人： Byung Je Lee ,  Byung Gil Yu ,  Nak Chung Choi ,  Chang Hwan Oh ,  Eun Duck Lee ,  Jong Hoon Park ,  Sun Byuong Park ,  Kyung Hun Kim

发明人： Byung Je Lee ,  Byung Gil Yu ,  Nak Chung Choi ,  Chang Hwan Oh ,  Eun Duck Lee ,  Jong Hoon Park ,  Sun Byuong Park ,  Kyung Hun Kim

IPC分类号： G06K19/077 ,  H01Q9/16

CPC分类号： H01Q1/2208 ,  H01Q9/16 ,  H01Q9/28 ,  H01Q9/285

摘要： The present invention relates to a radio frequency identification (RFID) tag antenna and an RFID tag, in which a connection part where a radiator dipole and a T-junction are connected has a branch structure, so that an electric current can be induced in the T-junction and the radiator dipole by the branch structure, and the amount of the electric current induced in the radiator dipole can be adjusted to thereby control impedance of the RFID tag antenna in detail. The RFID tag antenna includes: a substrate; a radiator dipole symmetrically printed on the substrate in a form of meanders; and a T-junction formed between the symmetrical radiator dipoles, formed integrally with each end part of the symmetrical radiator dipoles and performing impedance matching between the radiator dipole and an RFID tag chip, wherein a connection part where the symmetrical radiator dipole and the T-junction are connected has a branch structure.

摘要翻译： 射频识别（RFID）标签天线和RFID标签技术领域本发明涉及射频识别（RFID）标签天线和RFID标签，其中连接有散热器偶极和T形连接的连接部分具有分支结构，使得可以在 通过分支结构的T形结和散热器偶极子，并且可以调节在辐射器偶极子中感应的电流量，从而详细地控制RFID标签天线的阻抗。 RFID标签天线包括：基板; 以蜿蜒形式对称地印刷在基板上的散热器偶极子; 以及形成在对称的散热器偶极之间的T形接头，与对称的散热器偶极子的每个端部整体形成，并且执行辐射偶极子和RFID标签芯片之间的阻抗匹配，其中对称的散热器偶极子和T- 连接处有一个分支结构。

公开(公告)号：US20070049189A1

公开(公告)日：2007-03-01

申请号：US11463335

申请日：2006-08-09

申请人： Ho Beom LEE ,  Kyung Hwan KIM ,  Keun Hyoung CHOI ,  Dong Whan CHOI ,  Ho Seon CHOI ,  Jong Hoon PARK ,  Chang Hyun SONG

发明人： Ho Beom LEE ,  Kyung Hwan KIM ,  Keun Hyoung CHOI ,  Dong Whan CHOI ,  Ho Seon CHOI ,  Jong Hoon PARK ,  Chang Hyun SONG

IPC分类号： E06B7/02

CPC分类号： F24F13/24 ,  F24F7/007

摘要： A ventilator is provided. The ventilator includes blowers 60 and 70; ducts 62 and 72 that are connected to the blowers 60 and 70 to form a blow path having at least one bent part; and a sound-absorbing material 90 that is provided in the bent part of the blow path of the ducts 62 and 72 to absorb noise within the blow path thereof. Therefore, it is possible to remarkably reduce or prevent flow noise that is propagated to the inside of a room as noise of a flow passing through the ducts 62 and 72 is absorbed by the sound-absorbing material 90.

摘要翻译： 提供呼吸机。 呼吸机包括鼓风机60和70; 管道62和72，其连接到鼓风机60和70以形成具有至少一个弯曲部分的吹气路径; 以及吸气材料90，其设置在管道62和72的吹送路径的弯曲部分中以吸收其吹塑路径内的噪声。 因此，可以显着地减少或防止由于通过导管62和72的流动被吸声材料90所吸收的噪声而传播到房间内部的流动噪音。

公开(公告)号：US06765428B2

公开(公告)日：2004-07-20

申请号：US10028686

申请日：2001-12-28

申请人： Sun Min Kim ,  Jong-Hoon Park

发明人： Sun Min Kim ,  Jong-Hoon Park

IPC分类号： H03K301

CPC分类号： H02M3/073 ,  H02M2001/0032 ,  H02M2003/077 ,  Y02B70/16

摘要： A charge pump device for supplying a boosted voltage to a memory device includes a charge pump part constructed with first to nth unit charge pumps, and a multi-level detector for detecting a level of a boosted voltage to selectively drive the unit charge pumps in accordance with an amount of power consumption of the host and thereby outputting at least one level detection signal.

摘要翻译： 用于将升压电压提供给存储器件的电荷泵装置包括由第一至第n单位电荷泵构成的电荷泵部分，以及用于检测升压电压的电平以便按照按顺序驱动单元电荷泵的多电平检测器 具有主机的功耗量，从而输出至少一个电平检测信号。

公开(公告)号：US06339343B1

公开(公告)日：2002-01-15

申请号：US09407172

申请日：1999-09-28

申请人： Dong Kyeun Kim ,  Jong Hoon Park ,  San Ha Park

发明人： Dong Kyeun Kim ,  Jong Hoon Park ,  San Ha Park

IPC分类号： H03K90185

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096

摘要： A circuit controls data input/output buffers, where an input buffer is disabled during a read mode for reducing power consumption. In a preferred embodiment, a data input buffer is enabled in response to a control signal to receive data from an input/output pad. A data output buffer provides data to the input/output pad in response to the control signal. A data input/output buffer control unit generates the control signal to disable the data input buffer and enable the data output buffer in read mode. Preferably, the circuit is readily applicable to a memory device, such as a Synchronous Dynamic Random Access Memory (SDRAM).

摘要翻译： 电路控制数据输入/输出缓冲器，其中在读取模式下禁用输入缓冲器以降低功耗。 在优选实施例中，数据输入缓冲器响应于控制信号被使能以从输入/输出焊盘接收数据。 数据输出缓冲器响应于控制信号向输入/输出焊盘提供数据。 数据输入/输出缓冲器控制单元产生禁止数据输入缓冲器的控制信号，并以读出模式启用数据输出缓冲器。 优选地，该电路容易地应用于诸如同步动态随机存取存储器（SDRAM）的存储器件。

公开(公告)号：US06314038B1

公开(公告)日：2001-11-06

申请号：US09754119

申请日：2001-01-05

申请人： Jae-Woon Kim ,  Jong-Hoon Park

发明人： Jae-Woon Kim ,  Jong-Hoon Park

IPC分类号： G11C700

CPC分类号： G11C7/106 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18

摘要： A semiconductor memory includes a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells outputs a first data signal through an I/O line; an I/O line driving circuit for generating a second data signal by amplifying the first data signal, wherein the I/O line driving circuit is connected to the I/O lines; a data bus driving circuit connected to the I/O line driving circuit to generate a third data signal by amplifying the second data signal; a data bus precharge circuit; and a data bus connecting the data bus driving circuit to the data bus precharge circuit, wherein the data bus precharge circuit precharges the data bus to a predetermined voltage level before the third data signal is generated and transfers a voltage of the data bus to high or low level in accordance with a logic value of the third data signal when the third data signal is generated.

摘要翻译： 半导体存储器包括存储单元阵列，其包括多个存储单元，其中多个存储单元中的每一个通过I / O线输出第一数据信号; I / O线驱动电路，用于通过放大第一数据信号来产生第二数据信号，其中I / O线驱动电路连接到I / O线; 连接到I / O线驱动电路的数据总线驱动电路，通过放大第二数据信号产生第三数据信号; 数据总线预充电电路; 以及将数据总线驱动电路连接到数据总线预充电电路的数据总线，其中，数据总线预充电电路在产生第三数据信号之前将数据总线预充电到预定的电压电平，并将数据总线的电压传送到高或 当产生第三数据信号时，根据第三数据信号的逻辑值的低电平。

公开(公告)号：US5796663A

公开(公告)日：1998-08-18

申请号：US764444

申请日：1996-12-12

申请人： Jong Hoon Park ,  Tae Hyung Jung

发明人： Jong Hoon Park ,  Tae Hyung Jung

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/83

摘要： An address signal storage circuit of a data repair controller is disclosed including: a level stabilizer for stabilizing a level of an input signal to a constant level by a level control signal applied from the exterior according to the connection and disconnection of a fuse; a control signal generator for generating first and second control signals by a signal stabilized from the level stabilizer; and a signal storage portion for generating either a signal of a constant level by the first control signal generated from the control signal generator after disabled by a driving control signal applied from the exterior, or an inversion signal of the signal generated when disabled by storing an address signal of a prescribed level by the first and second control signals after enabled by the driving control signal.

公开(公告)号：US5654664A

公开(公告)日：1997-08-05

申请号：US623083

申请日：1996-03-28

申请人： Jong-Hoon Park ,  Jae-Woon Kim

发明人： Jong-Hoon Park ,  Jae-Woon Kim

IPC分类号： G11C11/417 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0948 ,  H01J19/82

CPC分类号： H03K19/0027

摘要： An input buffer circuit of a semiconductor memory capable of controlling a logic threshold voltage of the circuit according to a change in an external supply voltage, which includes an external supply voltage detecting unit for dividing the external supply voltage into a plurality of regions by comparing a plurality of voltages, which have been divided by different ratios of the entire external supply voltage, with a standard voltage; and a converting unit including a pull-up circuit and a pull-down circuit, for converting input signals of TTL level into signals of CMOS level, according to the regions of the external supply voltage obtained by the external supply voltage detecting unit. The input buffer has an advantage in that margins for a logical high input range and logical low input range are improved when converting voltages of TTL level into voltages of CMOS level, by controlling the logic threshold voltage so as to lower the logic threshold voltage when the external supply voltage level is high and raise the logic threshold voltage when the external supply voltage level is low.

摘要翻译： 一种半导体存储器的输入缓冲电路，其能够根据外部电源电压的变化来控制电路的逻辑阈值电压，该外部电源电压包括外部电源电压检测单元，用于将外部电源电压分为多个区域， 已经将整个外部电源电压的不同比例除以多个电压与标准电压; 以及包括上拉电路和下拉电路的转换单元，用于根据由外部电源电压检测单元获得的外部电源电压的区域将TTL电平的输入信号转换成CMOS电平的信号。 输入缓冲器的优点在于，当通过控制逻辑阈值电压将TTL电平的电压转换成CMOS电平的电压来改善逻辑高输入范围和逻辑低输入范围的裕度，从而当逻辑门限电压 外部电源电压高，外部电源电压低时提高逻辑门限电压。