公开(公告)号：US20140095849A1

公开(公告)日：2014-04-03

申请号：US13631402

申请日：2012-09-28

申请人： Polychronis Xekalakis ,  Pedro Marcuello ,  Alejandro Vicente Martinez ,  Christos E. Kotselidis ,  Grigorios Magklis ,  Fernando Latorre ,  Raul Martinez ,  Josep M. Codina ,  Enric Gibert Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Pedro Lopez ,  Marc Lupon ,  Carlos Madriles ,  Daniel Ortega ,  Demos Pavlou ,  Kyriakos A. Stavrou ,  Georgios Tournavitis

发明人： Polychronis Xekalakis ,  Pedro Marcuello ,  Alejandro Vicente Martinez ,  Christos E. Kotselidis ,  Grigorios Magklis ,  Fernando Latorre ,  Raul Martinez ,  Josep M. Codina ,  Enric Gibert Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Pedro Lopez ,  Marc Lupon ,  Carlos Madriles ,  Daniel Ortega ,  Demos Pavlou ,  Kyriakos A. Stavrou ,  Georgios Tournavitis

IPC分类号： G06F9/38

CPC分类号： G06F9/38 ,  G06F9/30036 ,  G06F9/3848 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/3889

摘要： A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.

摘要翻译： 描述了用于优化级感知分支预测的计算机可读存储介质，方法和系统。 齿轮级别被分配给已优化的一组应用指令。 齿轮级也存储在处理器的分支预测单元的寄存器中。 然后由处理器基于齿轮级执行分支预测。

公开(公告)号：US20130332705A1

公开(公告)日：2013-12-12

申请号：US13993054

申请日：2011-12-29

申请人： Raul Martinez ,  Enric Gibert Codina ,  Pedro Lopez ,  Marti Torrents Lapuerta ,  Polychronis Xekalakis ,  Georgios Tournavitis ,  Kyriakos A. Stavrou ,  Demos Pavlou ,  Daniel Ortega ,  Alejandro Martinez Vicente ,  Pedro Marcuello ,  Grigorios Magklis ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos Kotselidis ,  Fernando Latorre ,  Marc Lupon ,  Carlos Madriles

发明人： Raul Martinez ,  Enric Gibert Codina ,  Pedro Lopez ,  Marti Torrents Lapuerta ,  Polychronis Xekalakis ,  Georgios Tournavitis ,  Kyriakos A. Stavrou ,  Demos Pavlou ,  Daniel Ortega ,  Alejandro Martinez Vicente ,  Pedro Marcuello ,  Grigorios Magklis ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos Kotselidis ,  Fernando Latorre ,  Marc Lupon ,  Carlos Madriles

IPC分类号： G06F9/30

CPC分类号： G06F11/3037 ,  G06F11/3409 ,  G06F11/3466 ,  G06F12/0862 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2201/885

摘要： A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.

摘要翻译： 硬件和软件的组合以代码区域粒度收集用于异步事件的简档数据。 示例性实施例涉及收集在本质上是异步的预取事件的度量。 使用几种替代技术之一来标识属于代码区域的指令，使得为指令设置配置文件位作为标记。 预取数据块的每一行都被类似地标记。 然后识别与正在收集并且由代码区域内的指令产生的简档数据相对应的事件。 每次识别出不同类型的事件之一时，相应的计数器将被递增。 在代码区域中执行指令之后，收集在计数器中累积的简档数据，并且重置计数器以与新的代码区域一起使用。

公开(公告)号：US09811341B2

公开(公告)日：2017-11-07

申请号：US13995649

申请日：2011-12-29

申请人： Kyriakos A. Stavrou ,  Enric Gibert Codina ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos E. Kotselidis ,  Fernando Latorre ,  Pedro Lopez ,  Marc Lupon ,  Carlos Madriles Gimeno ,  Grigorios Magklis ,  Pedro Marcuello ,  Alejandro Martinez Vicente ,  Raul Martinez ,  Daniel Ortega ,  Demos Pavlou ,  Georgios Tournavitis ,  Polychronis Xekalakis

发明人： Kyriakos A. Stavrou ,  Enric Gibert Codina ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos E. Kotselidis ,  Fernando Latorre ,  Pedro Lopez ,  Marc Lupon ,  Carlos Madriles Gimeno ,  Grigorios Magklis ,  Pedro Marcuello ,  Alejandro Martinez Vicente ,  Raul Martinez ,  Daniel Ortega ,  Demos Pavlou ,  Georgios Tournavitis ,  Polychronis Xekalakis

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/0862

CPC分类号： G06F9/3804 ,  G06F9/30047 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3848 ,  G06F12/0862 ,  G06F2212/452

摘要： Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

公开(公告)号：US20140019721A1

公开(公告)日：2014-01-16

申请号：US13995649

申请日：2011-12-29

申请人： Kyriakos A. Stavrou ,  Enric Gibert Codina ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos E. Kotselidis ,  Fernando Latorre ,  Pedro Lopez ,  Marc Lupon ,  Carlos Madriles gimeno ,  Grigorios Magklis ,  Pedro Marcuello ,  Alejandro Martinez Vicente ,  Raul Martinez ,  Daniel Ortega ,  Demos Pavlou ,  Georgios Tournavitis ,  Polychronis Xekalakis

发明人： Kyriakos A. Stavrou ,  Enric Gibert Codina ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos E. Kotselidis ,  Fernando Latorre ,  Pedro Lopez ,  Marc Lupon ,  Carlos Madriles gimeno ,  Grigorios Magklis ,  Pedro Marcuello ,  Alejandro Martinez Vicente ,  Raul Martinez ,  Daniel Ortega ,  Demos Pavlou ,  Georgios Tournavitis ,  Polychronis Xekalakis

IPC分类号： G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/30047 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3848 ,  G06F12/0862 ,  G06F2212/452

摘要： Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: indentifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

摘要翻译： 公开了一种用于从指令高速缓存管理指令高速缓存预取的装置和方法。 处理器可以包括：预取引擎; 预测分支结果的分支预测引擎; 和动态优化器。 动态优化器可用于控制：识别公共指令高速缓存未命中并将预取引擎的预取指令插入指令高速缓存。

公开(公告)号：US20140156976A1

公开(公告)日：2014-06-05

申请号：US13995441

申请日：2011-12-22

申请人： Enric Gibert Codina ,  Josep M. Codina ,  Fernando Latorre ,  Pedro Marcuello ,  Pedro Lopez ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos E. Kotselidis ,  Marc Lupon ,  Carlos Madriles Gimeno ,  Grigorios Magklis ,  Alejandro Martinez Vicente ,  Raul Martinez ,  Daniel Ortega ,  Demos Pavlou ,  Kyriakos A. Stavrou ,  Georgios Tournavitis ,  Polychronis Xekalakis

发明人： Enric Gibert Codina ,  Josep M. Codina ,  Fernando Latorre ,  Pedro Marcuello ,  Pedro Lopez ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos E. Kotselidis ,  Marc Lupon ,  Carlos Madriles Gimeno ,  Grigorios Magklis ,  Alejandro Martinez Vicente ,  Raul Martinez ,  Daniel Ortega ,  Demos Pavlou ,  Kyriakos A. Stavrou ,  Georgios Tournavitis ,  Polychronis Xekalakis

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30087 ,  G06F9/30185 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863

摘要： Techniques and mechanisms for a processor to determine whether a commit action is to be performed. In an embodiment, a processor performs operations to determine whether a commit instruction is for contingent performance of a commit action. In another embodiment, one or more conditions of processor state are evaluated in response to determining that the commit instruction is for contingent performance of the commit action, where the evaluation is performed to determine whether the commit action indicated by the commit instruction is to be performed.

摘要翻译： 处理器确定是否执行提交动作的技术和机制。 在一个实施例中，处理器执行操作以确定提交指令是否用于或然执行提交动作。 在另一个实施例中，响应于确定提交指令用于提交动作的或然执行来评估处理器状态的一个或多个条件，其中执行评估以确定是否要执行由提交指令指示的提交动作 。

公开(公告)号：US20130326199A1

公开(公告)日：2013-12-05

申请号：US13995416

申请日：2011-12-29

申请人： Grigorios Magklis ,  Josep M. Codina ,  Craig B. Zilles ,  Michael Neilly ,  Sridhar Samudrala ,  Alejandro Martinez Vicente ,  Polychronis Xekalakis ,  F. Jesus Sanchez ,  Marc Lupon ,  Georgios Tournavitis ,  Enric Gibert Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos E. Kotselidis ,  Fernando Latorre ,  Pedro Lopez ,  Carlos Madriles Gimeno ,  Pedro Marcuello ,  Raul Martinez ,  Daniel Ortega ,  Demos Pavlou ,  Kyriakos A. Stavrou

发明人： Grigorios Magklis ,  Josep M. Codina ,  Craig B. Zilles ,  Michael Neilly ,  Sridhar Samudrala ,  Alejandro Martinez Vicente ,  Polychronis Xekalakis ,  F. Jesus Sanchez ,  Marc Lupon ,  Georgios Tournavitis ,  Enric Gibert Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos E. Kotselidis ,  Fernando Latorre ,  Pedro Lopez ,  Carlos Madriles Gimeno ,  Pedro Marcuello ,  Raul Martinez ,  Daniel Ortega ,  Demos Pavlou ,  Kyriakos A. Stavrou

IPC分类号： G06F9/30

CPC分类号： G06F9/3001 ,  G06F9/30032 ,  G06F9/30087 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3842

摘要： Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction.

摘要翻译： 公开了一种通常涉及控制多媒体扩展控制和状态寄存器（MXCSR）的装置和方法。 处理器核心可以包括用于执行算术功能的浮点单元（FPU） 以及为FPU提供控制位的多媒体扩展控制寄存器（MXCR）。 此外，优化器可以用于从多个SPEC_MXSR中选择推测性多媒体扩展状态寄存器（SPEC_MXSR），以基于指令来更新多媒体扩展状态寄存器（MXSR）。

公开(公告)号：US20090059913A1

公开(公告)日：2009-03-05

申请号：US11845813

申请日：2007-08-28

申请人： Jose Francisco Duato Marin ,  Francisco Gilabert Villamon ,  Crispin Gomez Requena ,  Maria Engracia Gomez Requena ,  Pedro Juan Lopez Rodriguez

发明人： Jose Francisco Duato Marin ,  Francisco Gilabert Villamon ,  Crispin Gomez Requena ,  Maria Engracia Gomez Requena ,  Pedro Juan Lopez Rodriguez

IPC分类号： H04L12/56

CPC分类号： H04L49/50 ,  H04L45/00 ,  H04L45/34 ,  H04L49/1507 ,  H04L49/358

摘要： The invention falls within the technology of multistage interconnection network such as fat-trees, comprising at least one switch located at a stage (s) and configured to send, through an output port from a number (k) of output ports forming an ordered list, at least a data packet containing a destination address identified by a n-tuple with a plurality (n) of components (pn−1, . . . , p1, p0), and sε{0 . . . (n−1)}. The invention has application for both source and distributed routing, as deterministic and as adaptive routing, selecting an output port to be the unique or the default option to forward the packets at the switch which is the output port that has a position in the ordered list of output ports corresponding to the component (ps) of the destination address at the position given by the stage (s) of the switch.

摘要翻译： 本发明属于诸如胖树之类的多级互连网络的技术，包括位于一个或多个阶段的至少一个交换机，并被配置为通过输出端口从数个（k）个输出端口发送，形成有序列表 至少包含由具有多个（n）个分量（pn-1，...，p1，p0）和sep（n）的n元组识别的目的地地址的数据分组。 。 。 （n-1）}。 本发明具有源和分布式路由的应用，作为确定性和自适应路由，选择输出端口是唯一或默认选项，以在作为排序列表中的位置的输出端口的交换机处转发数据包 的输出端口对应于由开关的级提供的位置处的目的地地址的分量（ps）。

公开(公告)号：US10013326B2

公开(公告)日：2018-07-03

申请号：US13993054

申请日：2011-12-29

申请人： Raul Martinez ,  Enric Gibert Codina ,  Pedro Lopez ,  Marti Torrents Lapuerta ,  Polychronis Xekalakis ,  Georgios Tournavitis ,  Kyriakos A. Stavrou ,  Demos Pavlou ,  Daniel Ortega ,  Alejandro Martinez Vicente ,  Pedro Marcuello ,  Grigorios Magklis ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos Kotselidis ,  Fernando Latorre ,  Marc Lupon ,  Carlos Madriles

发明人： Raul Martinez ,  Enric Gibert Codina ,  Pedro Lopez ,  Marti Torrents Lapuerta ,  Polychronis Xekalakis ,  Georgios Tournavitis ,  Kyriakos A. Stavrou ,  Demos Pavlou ,  Daniel Ortega ,  Alejandro Martinez Vicente ,  Pedro Marcuello ,  Grigorios Magklis ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos Kotselidis ,  Fernando Latorre ,  Marc Lupon ,  Carlos Madriles

IPC分类号： G06F11/30 ,  G06F11/34 ,  G06F12/0862

CPC分类号： G06F11/3037 ,  G06F11/3409 ,  G06F11/3466 ,  G06F12/0862 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2201/885

摘要： A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.

公开(公告)号：US20130268735A1

公开(公告)日：2013-10-10

申请号：US13994686

申请日：2011-12-29

申请人： Enric Gibert Codina ,  Fernando Latorre ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Meyrem Hyuseinova ,  Christos E. Kotselidis ,  Pedro Lopez ,  Marc Lupon ,  Carlos Madriles ,  Grigorios Magklis ,  Pedro Marcuello ,  Alejandro Martinez Vicente ,  Raul Martinez ,  Daniel Ortega ,  Demos Pavlou ,  Kyriakos A. Stavrou ,  Georgios Tournavitis ,  Polychronis Xekalakis

发明人： Enric Gibert Codina ,  Fernando Latorre ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Meyrem Hyuseinova ,  Christos E. Kotselidis ,  Pedro Lopez ,  Marc Lupon ,  Carlos Madriles ,  Grigorios Magklis ,  Pedro Marcuello ,  Alejandro Martinez Vicente ,  Raul Martinez ,  Daniel Ortega ,  Demos Pavlou ,  Kyriakos A. Stavrou ,  Georgios Tournavitis ,  Polychronis Xekalakis

IPC分类号： G06F12/08

CPC分类号： G06F12/0815 ,  G06F2212/507

摘要： Techniques are described for providing an enhanced cache coherency protocol for a multi-core processor that includes a Speculative Request For Ownership Without Data (SRFOWD) for a portion of cache memory. With a SRFOWD, only an acknowledgement message may be provided as an answer to a requesting core. The contents of the affected cache line are not required to be a part of the answer. The enhanced cache coherency protocol may assure that a valid copy of the current cache line exists in case of misspeculation by the requesting core. Thus, an owner of the current copy of the cache line may maintain a copy of the old contents of the cache line. The old contents of the cache line may be discarded if speculation by the requesting core turns out to be correct. Otherwise, in case of misspeculation by the requesting core, the old contents of the cache line may be set back to a valid state.

摘要翻译： 描述了用于为多核处理器提供增强的高速缓存一致性协议的技术，所述多核处理器包括用于高速缓冲存储器的一部分的无数据的投机请求（SRFOWD）。 使用SRFOWD，可以仅提供确认消息作为请求内核的答案。 受影响的缓存行的内容不需要作为答案的一部分。 增强的高速缓存一致性协议可以确保在请求核心的错误配置的情况下存在当前高速缓存行的有效副本。 因此，高速缓存行的当前副本的所有者可以维护高速缓存行的旧内容的副本。 如果请求的核心的推测证明是正确的，则可以丢弃该高速缓存行的旧内容。 否则，在请求核心发生错误的情况下，可以将高速缓存行的旧内容设置回有效状态。

公开(公告)号：US08085659B2

公开(公告)日：2011-12-27

申请号：US11845813

申请日：2007-08-28

申请人： Jose Francisco Duato Marin ,  Francisco Gilabert Villamon ,  Crispin Gomez Requena ,  Maria Engracia Gomez Requena ,  Pedro Juan Lopez Rodriguez

发明人： Jose Francisco Duato Marin ,  Francisco Gilabert Villamon ,  Crispin Gomez Requena ,  Maria Engracia Gomez Requena ,  Pedro Juan Lopez Rodriguez

IPC分类号： G01R31/08 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26 ,  H04L12/28

CPC分类号： H04L49/50 ,  H04L45/00 ,  H04L45/34 ,  H04L49/1507 ,  H04L49/358

摘要： The invention falls within the technology of multistage interconnection network such as fat-trees, comprising at least one switch located at a stage (s) and configured to send, through an output port from a number (k) of output ports forming an ordered list, at least a data packet containing a destination address identified by a n-tuple with a plurality (n) of components (pn−1, . . . , p1, p0), and sε{0 . . . (n−1)}. The invention has application for both source and distributed routing, as deterministic and as adaptive routing, selecting an output port to be the unique or the default option to forward the packets at the switch which is the output port that has a position in the ordered list of output ports corresponding to the component (ps) of the destination address at the position given by the stage (s) of the switch.

摘要翻译： 本发明属于诸如胖树之类的多级互连网络的技术，包括位于一个或多个阶段的至少一个交换机，并被配置为通过输出端口从数个（k）个输出端口发送，形成有序列表 至少包含由具有多个（n）个分量（pn-1，...，p1，p0）的n元组识别的目的地地址的数据分组，以及s＆egr; {0。 。 。 （n-1）}。 本发明具有源和分布式路由的应用，作为确定性和自适应路由，选择输出端口是唯一或默认选项，以在作为排序列表中的位置的输出端口的交换机处转发数据包 的输出端口对应于由开关的级提供的位置处的目的地地址的分量（ps）。