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7 条记录 (耗时 0.014 秒)

    Bootstrap buffer
    2.
    发明授权
    Bootstrap buffer 失效
    引导缓冲区

    公开(公告)号：US4649300A

    公开(公告)日：1987-03-10

    申请号：US764494

    申请日：1985-08-12

    申请人： Joseph D. Schutz

    发明人： Joseph D. Schutz

    IPC分类号： H03K19/096 ,  H03K5/02 ,  H03K17/06 ,  H03K19/017 ,  H03K4/58 ,  H03K17/04 ,  H03K17/687

    CPC分类号： H03K19/01714

    摘要： A bootstrapped driver particularly suitable for CMOS integrated circuits. The circuit permits precharging of gates which require bootstrapping in the driver, thus avoiding the time required in prior art circuits to charge relatively large gate capacitance after the input signal is applied to the driver. A circuit is provided to reduce the bootstrapping of the gate after it has begun to reduce possible gate edge aided breakdown. Substantial improvement in rise time or fall time is achieved.

    摘要翻译： 自举驱动器特别适用于CMOS集成电路。 电路允许在驱动器中需要自举的门的预充电，从而避免了现有技术电路在将输入信号施加到驱动器之后对相对较大的栅极电容充电所需的时间。 提供电路以在栅极开始减少可能的栅极边缘辅助击穿之后减小栅极的自举。 实现了上升时间或下降时间的显着改善。

    Integrated circuit device that selects its own supply voltage by controlling a power supply
    5.
    发明授权
    Integrated circuit device that selects its own supply voltage by controlling a power supply 失效
    集成电路设备，通过控制电源选择自己的电源电压

    公开(公告)号：US5440520A

    公开(公告)日：1995-08-08

    申请号：US307190

    申请日：1994-09-16

    申请人： Joseph D. Schutz ,  Bill C. Rash

    发明人： Joseph D. Schutz ,  Bill C. Rash

    IPC分类号： G11C5/14 ,  H03K19/003 ,  G11C7/04

    CPC分类号： H03K19/00369 ,  G11C5/143 ,  Y10S323/907

    摘要： The specification describes an integrated circuit device that selects its own supply voltage by controlling a programmable power supply. The programmable power supply provides a supply voltage in response to one or more voltage control signals generated by the integrated circuit device. The integrated circuit device includes a voltage control circuit for generating the voltage control signals according to one or more predetermined operational voltages programmed into the integrated circuit device such that the supply voltage is substantially equal to a selected one of the predetermined operational voltages. The integrated circuit device may include a temperature sensor to allow selection of the predetermined operational voltage according to device temperature to avoid speed-limiting voltage and temperature combinations.

    摘要翻译： 本说明书描述了通过控制可编程电源来选择其自身电源电压的集成电路器件。 可编程电源响应于由集成电路器件产生的一个或多个电压控制信号而提供电源电压。 集成电路装置包括电压控制电路，用于根据编程到集成电路装置中的一个或多个预定操作电压产生电压控制信号，使得电源电压基本上等于所选择的一个预定操作电压。 集成电路装置可以包括温度传感器，以允许根据装置温度选择预定的工作电压，以避免速度限制的电压和温度组合。

    CMOS dynamic random-access memory with active cycle one half power supply potential bit line precharge
    6.
    发明授权
    CMOS dynamic random-access memory with active cycle one half power supply potential bit line precharge 失效
    CMOS动态随机存取存储器，带有活动周期的一半电源电位位线预充电

    公开(公告)号：US4584672A

    公开(公告)日：1986-04-22

    申请号：US582526

    申请日：1984-02-22

    申请人： Joseph D. Schutz ,  Roger I. Kung

    发明人： Joseph D. Schutz ,  Roger I. Kung

    IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C11/4094 ,  G11C7/00

    CPC分类号： G11C11/4094

    摘要： A CMOS dynamic RAM is described which uses multiplexing to selectively couple two pairs of bit lines to a single sense amplifier. Both pairs of bit lines are decoupled from the sense amplifier after a word line selects a cell and before sensing occurs in the sense amplifier. Only one pair of bit lines is coupled to the input/output lines of the memory. No dummy cells are employed. The bit lines are charged to one-half the power supply potential. Restoration of potentials on each pair of bit lines occurs at different times, thereby reducing the peak currents to the RAM.

    摘要翻译： 描述了使用多路复用来选择性地将两对位线耦合到单个读出放大器的CMOS动态RAM。 在字线选择一个单元之后并且在感测放大器中发生感测之前，两对位线都与读出放大器去耦。 只有一对位线耦合到存储器的输入/输出线。 没有使用虚拟细胞。 位线被充电到电源电位的一半。 每对位线上的电位的恢复发生在不同的时间，从而减少到RAM的峰值电流。

    Power up reset circuit
    7.
    发明授权
    Power up reset circuit 失效
    上电复位电路

    公开(公告)号：US5111067A

    公开(公告)日：1992-05-05

    申请号：US692487

    申请日：1991-04-29

    申请人： Keng L. Wong ,  Joseph D. Schutz

    发明人： Keng L. Wong ,  Joseph D. Schutz

    IPC分类号： G06F1/24 ,  H03K17/22

    CPC分类号： H03K17/223

    摘要： A global reset circuit especially suitable for integration into a microprocessor and implemented in CMOS technology is disclosed herein. This circuit includes reset circuitry having an input adapted for connection with a direct current power supply voltage which, when activated, rises from its minimum voltage level to its maximum voltage level over a period of time, and an output adapted for connection with at least one circuit component to be reset, for example certain components forming part of a microprocessor. To this end, the circuitry provides a reset signal at its output upon initiation of the power supply voltage and until the power supply voltage reaches a predetermined level, at which time the reset signal is removed. A latching circuit which forms part of the reset circuitry is operated by the power supply voltage in a first state during the presence of the reset signal and in a second, latched state for removing the reset signal. The latching circuit operates in its second, latched state so long as the supply voltage remains above the predetermined level. Means also forming part of the reset circuitry is provided for grounding the latching circuit through a predetermined resistance.

    摘要翻译： 本文公开了特别适用于集成到微处理器中并以CMOS技术实现的全局复位电路。 该电路包括复位电路，其具有适于与直流电源电压连接的输入，该直流电源电压在被激活时在一段时间内从其最小电压电平上升到其最大电压电平，以及适于与至少一个 电路元件被复位，例如形成微处理器的一部分的某些元件。 为此，电路在电源电压开始时在其输出端提供复位信号，直到电源电压达到预定电平，此时复位信号被去除。 形成复位电路的一部分的锁存电路在存在复位信号期间由第一状态的电源电压和用于去除复位信号的第二锁存状态来操作。 只要电源电压保持在预定电平以上，锁存电路就工作在其第二个锁存状态。 还构成复位电路的一部分的装置被提供用于通过预定电阻使锁存电路接地。