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1.发明授权Microprocessor having single poly-silicon EPROM memory for programmably controlling optional features 失效具有单个多晶硅EPROM存储器的微处理器，可编程控制可选功能
公开(公告)号：US5732207A
公开(公告)日：1998-03-24
申请号：US396117
申请日：1995-02-28
申请人： Michael J. Allen , Gregory K. Crain , Stephen A. Fischer , Patrick P. Gelsinger , David R. Gray , Stuart T. Hopkins , Gustav Laub, III , Charles H. Lucas , Richard D. Pashley , Babak Sabi , Joseph D. Schutz , David J. Shield , Stephen F. Sullivan
发明人： Michael J. Allen , Gregory K. Crain , Stephen A. Fischer , Patrick P. Gelsinger , David R. Gray , Stuart T. Hopkins , Gustav Laub, III , Charles H. Lucas , Richard D. Pashley , Babak Sabi , Joseph D. Schutz , David J. Shield , Stephen F. Sullivan
CPC分类号： G11C29/76 , G06F11/006 , G06F15/7814 , G11C29/44 , G11C29/789
摘要： A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process-compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.
摘要翻译： CMOS微处理器芯片包括与用于制造微处理器的CMOS工艺处理兼容的片上单聚EPROM。 EPROM用于存储制造和合同相关数据，如序列号，客户和过程相关数据，如晶圆号测试结果，合并数据等。这为质量和可靠性控制提供了重要信息。 EPROM还用于控制可选微处理器功能的选择，如速度调节，引脚输出和I / O总线接口配置。 第三种用途是修剪关键电路元件和缓存冗余故障控制。
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2.发明授权Microprocessor having single poly-silicon EPROM memory for programmably controlling optional features 失效具有单个多晶硅EPROM存储器的微处理器，可编程控制可选功能
公开(公告)号：US5852712A
公开(公告)日：1998-12-22
申请号：US925527
申请日：1997-09-08
申请人： Michael J. Allen , Gregory K. Crain , Stephen A. Fischer , Patrick P. Gelsinger , David R. Gray , Stuart T. Hopkins , Gustay Laub, III , Charles H. Lucas , Richard D. Pashley , Babak Sabi , Joseph D. Schutz , David J. Shield , Stephen F. Sullivan
发明人： Michael J. Allen , Gregory K. Crain , Stephen A. Fischer , Patrick P. Gelsinger , David R. Gray , Stuart T. Hopkins , Gustay Laub, III , Charles H. Lucas , Richard D. Pashley , Babak Sabi , Joseph D. Schutz , David J. Shield , Stephen F. Sullivan
CPC分类号： G11C29/76 , G06F11/006 , G06F15/7814 , G11C29/44 , G11C29/789
摘要： A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.
摘要翻译： CMOS微处理器芯片包括与用于制造微处理器的CMOS工艺兼容的片上单聚EPROM。 EPROM用于存储制造和合同相关数据，如序列号，客户和过程相关数据，如晶圆号测试结果，合并数据等。这为质量和可靠性控制提供了重要信息。 EPROM还用于控制可选微处理器功能的选择，如速度调节，引脚输出和I / O总线接口配置。 第三种用途是修剪关键电路元件和缓存冗余故障控制。
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3.发明授权Method and apparatus for a non-deterministic random bit generator (NRBG) 有权用于非确定性随机位发生器（NRBG）的方法和装置公开(公告)号：US09544139B2
公开(公告)日：2017-01-10
申请号：US13976175
申请日：2011-12-29
CPC分类号： H04L9/0869 , G06F7/588 , G06F9/30007 , H04L9/0662 , H04L2209/24
摘要： A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings, and an execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction.
摘要翻译： 提供了一种基于硬件的数字随机数发生器。 在一个实施例中，处理器包括数字随机数发生器（DRNG），用于对熵源提供的熵数据进行条件生成，以产生多个确定性随机位（DRB）串，并产生多个非确定性随机位（NRB） 响应于读取种子值的第一指令，从DRNG检索NRB字符串中的一个并将NRB字符串存储在由第一指令指定的目的地寄存器中，耦合到DRNG的执行单元。
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公开(公告)号：US20160098075A1
公开(公告)日：2016-04-07
申请号：US14966708
申请日：2015-12-11
申请人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
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公开(公告)号：US20140123286A1
公开(公告)日：2014-05-01
申请号：US13799663
申请日：2013-03-13
IPC分类号： G06F21/56
CPC分类号： G06F21/552 , G06F9/30145 , G06F21/566 , G06F2221/034
摘要： In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.
摘要翻译： 在一个实施例中，处理器包括至少一个执行单元和返回定向编程（ROP）检测逻辑。 ROP检测逻辑可以基于多个控制传送事件来确定ROP度量。 ROP检测逻辑还可以确定ROP度量是否超过阈值。 ROP检测逻辑还可以响应于ROP度量超过阈值的确定，提供ROP攻击通知。
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公开(公告)号：US08489660B2
公开(公告)日：2013-07-16
申请号：US12459142
申请日：2009-06-26
申请人： Howard C. Herbert , George W. Cox , Shay Gueron , Jesse Walker , Charles E. Dike , Stephen A. Fischer , Ernie Brickell , Martin G. Dixon , David Johnston , Gunendran Thuraisingham , Edward V. Gamsaragan , James S. Coke , Greg W. Piper
发明人： Howard C. Herbert , George W. Cox , Shay Gueron , Jesse Walker , Charles E. Dike , Stephen A. Fischer , Ernie Brickell , Martin G. Dixon , David Johnston , Gunendran Thuraisingham , Edward V. Gamsaragan , James S. Coke , Greg W. Piper
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F9/30007 , H04L9/0861
摘要： A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source “extra” bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.
摘要翻译： 提供了一种基于硬件的数字随机数发生器。 数字随机数发生器是基于一组非确定性行为的随机行为随机数发生器。 非确定性行为包括子单元之间的时间不同步，熵源“额外”比特，熵测量，自主确定性随机比特生成器重新获取和来自共享资源的消费。
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公开(公告)号：US08230203B2
公开(公告)日：2012-07-24
申请号：US11694344
申请日：2007-03-30
申请人： Gilbert Neiger , Randolph L. Campbell , James B. Crossland , Gideon Gerzon , Leena K. Puthiyedath , Stephen A. Fischer , Steven M. Bennett , Andrew V. Anderson
发明人： Gilbert Neiger , Randolph L. Campbell , James B. Crossland , Gideon Gerzon , Leena K. Puthiyedath , Stephen A. Fischer , Steven M. Bennett , Andrew V. Anderson
CPC分类号： G06F9/45533
摘要： Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the apparatus from the guest to a host in response to the detection logic detecting that the guest is executing the spin loop.
摘要翻译： 公开了在虚拟机环境中检测自旋回路的装置，方法和系统的实施例。 在一个实施例中，装置包括检测逻辑和虚拟逻辑。 检测逻辑是检测访客是否正在执行自旋循环。 响应于检测到客户正在执行自旋回路的检测逻辑，虚拟化逻辑是将设备的控制从客户转移到主机。
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8.发明授权Method and system for accessing memory in parallel computing using load fencing instructions 有权使用负载击剑指令并行计算访问存储器的方法和系统公开(公告)号：US08171261B2
公开(公告)日：2012-05-01
申请号：US10654573
申请日：2003-09-02
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
摘要翻译： 一种用于防止内存访问的系统和方法。 存储器负载可以围栏，或者所有内存访问都可以被围起来。 系统接收一个将内存访问指令分为较早访问和较新访问的防护指令。 存储器排序单元内的缓冲器被分配给该指令。 比栅栏指令更新的访问指令被停止。 旧的访问指令已逐渐退出。 当所有较旧的内存访问都已停用时，从缓冲区中分派防护指令。
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公开(公告)号：US20100146311A1
公开(公告)日：2010-06-10
申请号：US12706631
申请日：2010-02-16
申请人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
IPC分类号： G06F1/00
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
摘要翻译： 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。
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公开(公告)号：US06898700B2
公开(公告)日：2005-05-24
申请号：US09053398
申请日：1998-03-31
申请人： William C. Alexander, III , Shreekant S. Thakkar , Patrice L. Roussel , Thomas Huff , Bryant E. Bigbee , Stephen A. Fischer
发明人： William C. Alexander, III , Shreekant S. Thakkar , Patrice L. Roussel , Thomas Huff , Bryant E. Bigbee , Stephen A. Fischer
CPC分类号： G06F9/30043 , G06F9/462
摘要： The present invention discloses a method and apparatus for saving and restoring registers. A single instruction is decoded. The single instruction moves contents of a plurality of registers associated with a functional unit in a processor to a memory; the processor operates under a plurality of operational modes and operand sizes. The single instruction arranges the contents in the memory according to a predetermined format into a plurality of groups, each group is aligned at an address boundary which corresponds to a multiple of 2N bytes. The predetermined format is constant for the plurality of operational modes and operand sizes. The single instruction retains the contents of the plurality of registers after moving.
摘要翻译： 本发明公开了一种保存和恢复寄存器的方法和装置。 单个指令被解码。 单个指令将与处理器中的功能单元相关联的多个寄存器的内容移动到存储器; 处理器在多种操作模式和操作数大小下工作。 单个指令根据预定格式将内容排列到多个组中，每组在对应于2×N个字节的倍数的地址边界对齐。 对于多个操作模式和操作数大小，预定格式是恒定的。 单指令在移动后保留多个寄存器的内容。
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