公开(公告)号：US5365073A

公开(公告)日：1994-11-15

申请号：US80730

申请日：1993-06-24

申请人： Julian D. White

发明人： Julian D. White

IPC分类号： B82B1/00 ,  B82B3/00 ,  G01Q60/00 ,  G01Q80/00 ,  G11B9/00 ,  H01J37/30 ,  H01L21/28 ,  H01L29/76 ,  H01L49/00 ,  H01J37/305

CPC分类号： B82B1/00 ,  B82B3/00 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L29/7613 ,  H01L49/00 ,  G01Q80/00 ,  G11B9/14 ,  Y10S977/859 ,  Y10S977/861 ,  Y10S977/951

摘要： A method of forming a nano-scale device with a probe (2) such as a STM on a substrate (1) includes the step of rendering the relevant part of the substrate conductive while the device (5) is being formed with the probe so that current can flow from the probe to the substrate. Thereafter, to operate the device, the substrate is rendered non-conductive so as to prevent dissipation of current from the device through the substrate. The substrate can be altered in conductivity by cooling to undergo a Mott transition, can be heated from a normally non-conductive condition to become conductive, or subjected to laser radiation to induce charge carriers to render it conductive.

摘要翻译： 在衬底（1）上形成具有诸如STM的探针（2）的纳米级器件的方法包括在器件（5）正在形成探针的同时使衬底的相关部分导通的步骤 该电流可以从探针流到衬底。 此后，为了操作该器件，使衬底不导电，以防止电流从器件通过衬底的散逸。 可以通过冷却改变导电性以进行莫特转变，可以从正常非导电状态加热成导电性，或者进行激光辐射以引起电荷载体使其导电。

公开(公告)号：US5677637A

公开(公告)日：1997-10-14

申请号：US606835

申请日：1996-02-27

申请人： Kazuo Nakazato ,  Haroon Ahmed ,  Julian D. White

发明人： Kazuo Nakazato ,  Haroon Ahmed ,  Julian D. White

IPC分类号： G01R29/12 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/56 ,  G11C19/18 ,  H03K19/08 ,  H03K19/23 ,  H03K19/00

CPC分类号： B82Y10/00 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/56 ,  G11C19/182 ,  H03K19/08 ,  G01R29/12 ,  G11C2216/08 ,  Y10S977/937

摘要： A memory device includes a memory node (2) to which is connected a tunnel barrier configuration such that the node exhibits first and second quantized memory states for which the level of stored charge is limited by Coulomb Blockade and a surplus or shortfall of a small number of electrons for example ten electrons or even a single electron can be used to represent quantized memory states. A series of the nodes N0-N3 that are interconnected by tunnel barriers D can be arranged as a logic device. Clock waveforms V1-V3 applied to clock lines C1 1-C1 3 selectively alter the probability of charge carriers passing through the tunnel diodes D from node to node. An output device, typically a Coulomb blockade electrometer provides an output logical signal indicative of the logical state of node N3. Arrays of separately addressable memory cells M.sub.mn are also described, that utilize gated multiple tunnel junctions (MTJs) as their barrier configurations. Side gated GaAs MTJ structures formed by selective etching and lithography are described. Also, gate structures which modulate a conductive channel with depletion regions to form multiple tunnel junctions are disclosed.

摘要翻译： 存储器装置包括存储器节点（2），其连接有隧道势垒配置，使得节点具有第一和第二量化的存储器状态，存储电荷的级别由库仑阻塞限制，少量或少量的少量 的电子，例如十个电子或甚至单个电子可以用于表示量化的记忆状态。 通过隧道屏障D互连的一系列节点N0-N3可以被布置为逻辑设备。 施加到时钟线C1 1 -C1 3的时钟波形V1-V3选择性地改变从节点到节点通过隧道二极管D的电荷载流子的概率。 输出装置（通常是库仑阻塞静电计）提供指示节点N3的逻辑状态的输出逻辑信号。 还描述了单独可寻址存储器单元Mmn的阵列，其利用门控多隧道结（MTJ）作为其屏障配置。 描述了通过选择性蚀刻和光刻形成的侧栅GaAs MTJ结构。 此外，公开了用耗尽区调制导电沟道以形成多个隧道结的栅极结构。