公开(公告)号：US09967547B2

公开(公告)日：2018-05-08

申请号：US15484609

申请日：2017-04-11

Applicant: QUALCOMM Incorporated

Inventor： Todor Georgiev Georgiev ,  Zheng-wu Li ,  Wen-Yu Sun

IPC: H04N13/02 ,  G02B13/04 ,  G02B27/00 ,  H01L27/146 ,  G02B27/22 ,  H01L49/00 ,  G02B13/00 ,  H04N5/225 ,  H04N5/378

CPC classification number: H04N13/279 ,  G02B13/0065 ,  G02B13/0085 ,  G02B13/04 ,  G02B27/0025 ,  G02B27/22 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/1464 ,  H01L49/00 ,  H04N5/2254 ,  H04N5/378 ,  H04N13/218 ,  H04N13/271

Abstract: Certain aspects relate to wafer level optical designs for a folded optic stereoscopic imaging system. One example folded optical path includes first and second reflective surfaces defining first, second, and third optical axes, and where the first reflective surface redirects light from the first optical axis to the second optical axis and where the second reflective surface redirects light from the second optical axis to the third optical axis. Such an example folded optical path further includes wafer-level optical stacks providing ten lens surfaces distributed along the first and second optical axes. A variation on the example folded optical path includes a prism having the first reflective surface, wherein plastic lenses are formed in or secured to the input and output surfaces of the prism in place of two of the wafer-level optical stacks.

公开(公告)号：US09954167B2

公开(公告)日：2018-04-24

申请号：US15266181

申请日：2016-09-15

Applicant: Toshiba Memory Corporation

Inventor： Shosuke Fujii ,  Takayuki Ishikawa

IPC: H01L45/00 ,  H01L27/105 ,  H01L49/00

CPC classification number: H01L45/14 ,  G11C13/0007 ,  H01L27/105 ,  H01L27/2436 ,  H01L45/00 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1253 ,  H01L45/146 ,  H01L49/00

Abstract: According to one embodiment, a memory device includes a first layer, a second layer, and a third layer provided between the first layer and the second layer. The first layer includes first interconnections and a first insulating portion. The first interconnections extend in a first direction. The first insulating portion is provided between the first interconnections. The second layer includes a plurality of second interconnections and a second insulating portion. The second interconnections extend in a second direction crossing the first direction. The second insulating portion is provided between the second interconnections. The third layer includes a ferroelectric portion and a paraelectric portion. The ferroelectric portion and the paraelectric portion include hafnium oxide.

公开(公告)号：US20180025765A1

公开(公告)日：2018-01-25

申请号：US15520932

申请日：2015-10-23

Applicant: Sony Corporation

Inventor： Takashi Yokoyama ,  Shunsaku Tokito ,  Hiroshi Hasegawa ,  Hajime Yamagishi

IPC: G11C11/16 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  H01L43/02

CPC classification number: G11C11/1697 ,  G11C14/0081 ,  H01L27/105 ,  H01L27/11 ,  H01L27/228 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00 ,  H01L49/00

Abstract: A semiconductor device includes a flip-flop circuit, a control line, a first P-type transistor and a first non-volatile storage element, and a second P-type transistor and a second non-volatile storage element. The flip-flop circuit has a circular structure in which a first inverter circuit, a first connection line including a first node, a second inverter circuit, and a second connection line including a second node are coupled in order. The first P-type transistor and the first non-volatile storage element are coupled together in series between the first node and the control line. The second P-type transistor and the second non-volatile storage element are coupled together in series between the second node and the control line. The non-volatile storage element is a magnetic tunnel junction element including a pinned layer, a tunnel barrier layer, and a free layer arranged in order from a position close to the control line.

公开(公告)号：US20170358658A1

公开(公告)日：2017-12-14

申请号：US15506205

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Rafael RIOS ,  Kelin J. KUHN ,  Seiyon KIM ,  Justin R. Weber

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66439 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/122 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78636 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  H01L49/00

Abstract: Embodiments of the invention include metal oxide metal field effect transistors (MOMFETs) and methods of making such devices. In embodiments, the MOMFET device includes a source and a drain with a channel disposed between the source and the drain. According to an embodiment, the channel has at least one confined dimension that produces a quantum confinement effect in the channel. In an embodiment, the MOMFET device also includes a gate electrode that is separated from the channel by a gate dielectric. According to embodiments, the band-gap energy of the channel may be modulated by changing the size of the channel, the material used for the channel, and/or the surface termination applied to the channel. Embodiments also include forming an type device and a P-type device by controlling the work-function of the source and drain relative to the conduction band and valance band energies of the channel.

公开(公告)号：US20170315074A1

公开(公告)日：2017-11-02

申请号：US15483319

申请日：2017-04-10

Applicant: Robert Bosch GmbH

Inventor： Matthias Christian Schwille

IPC: G01N27/12

CPC classification number: G01N27/121 ,  G01N27/225 ,  H01L49/00

Abstract: A micromechanical moisture-sensor device and a corresponding manufacturing method. The micromechanical moisture-sensor device is equipped with a first electrode device situated on the substrate; a second electrode device situated on the substrate; an electrical insulation device situated between the first electrode device and the second electrode device which includes a first area, which is in contact with the first electrode device and the second electrode device, and which includes a second area, which is exposed by the first electrode device and the second electrode device; a moisture-sensitive functional layer, which is applied across the first electrode device and the second electrode device and the second area of the insulation device lying between them in such a way that it forms a moisture-sensitive resistive electrical shunt at least in some areas between the first electrode device and the second electrode device.

公开(公告)号：US09793477B2

公开(公告)日：2017-10-17

申请号：US14137840

申请日：2013-12-20

Applicant: The Regents of the University of California

Inventor： Daojing Wang ,  Pan Mao ,  Hung-Ta Wang ,  Peidong Yang

IPC: H01L49/00 ,  B01D59/44 ,  G01N30/72 ,  B01D3/00 ,  H01J49/04 ,  H01J49/00 ,  H01J49/16 ,  B01L3/00

CPC classification number: H01L49/00 ,  B01D59/44 ,  B01L3/5027 ,  G01N30/72 ,  G01N30/7206 ,  H01J49/0018 ,  H01J49/04 ,  H01J49/167

Abstract: The present invention provides for a structure comprising a plurality of emitters, wherein a first nozzle of a first emitter and a second nozzle of a second emitter emit in two directions that are not or essentially not in the same direction; wherein the walls of the nozzles and the emitters form a monolithic whole. The present invention also provides for a structure comprising an emitter with a sharpened end from which the emitter emits; wherein the emitters forms a monolithic whole. The present invention also provides for a fully integrated separation of proteins and small molecules on a silicon chip before the electrospray mass spectrometry analysis.

公开(公告)号：US20170012199A1

公开(公告)日：2017-01-12

申请号：US15203773

申请日：2016-07-06

Applicant: Si-Ware Systems

Inventor： Yasser M. Sabry ,  Diaa Khalil ,  Tarik E. Bourouina ,  Momen Anwar

IPC: H01L49/00

CPC classification number: H01L49/00 ,  G01J3/0205 ,  G01J3/0208 ,  G01J3/0216 ,  G01J3/0237 ,  G01J3/0245 ,  G01J3/108 ,  G01J3/26 ,  G01J3/42 ,  H01K1/04 ,  H01K1/14

Abstract: An optical radiation source produced from a disordered semiconductor material, such as black silicon, is provided. The optical radiation source includes a semiconductor substrate, a disordered semiconductor structure etched in the semiconductor substrate and a heating element disposed proximal to the disordered semiconductor structure and configured to heat the disordered semiconductor structure to a temperature at which the disordered semiconductor structure emits thermal infrared radiation.

Abstract translation: 提供由诸如黑色硅的无序半导体材料产生的光辐射源。 光辐射源包括半导体衬底，在半导体衬底中蚀刻的无序半导体结构和设置在无序半导体结构附近的加热元件，其被配置为将无序半导体结构加热到无序半导体结构发射热红外辐射的温度 。

公开(公告)号：US09425381B2

公开(公告)日：2016-08-23

申请号：US14468822

申请日：2014-08-26

Applicant: International Business Machines Corporation

Inventor： Bruce G. Elmegreen ,  Glenn J. Martyna ,  Dennis M. Newns

IPC: H01L41/083 ,  H01L41/18 ,  H01L41/047

CPC classification number: H01L41/107 ,  H01L41/047 ,  H01L41/0472 ,  H01L41/083 ,  H01L41/183 ,  H01L41/1876 ,  H01L49/00

Abstract: A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.

公开(公告)号：US09419203B2

公开(公告)日：2016-08-16

申请号：US14747223

申请日：2015-06-23

Applicant: International Business Machines Corporation

Inventor： Brian A. Bryce ,  Josephine B. Chang ,  Matthew W. Copel ,  Marcelo A. Kuroda

IPC: H01L29/84 ,  H01L41/083 ,  H01L41/047

CPC classification number: H01L41/083 ,  H01L41/0477 ,  H01L41/107 ,  H01L41/314 ,  H01L41/332 ,  H01L49/00

Abstract: A method of forming a piezoelectronic transistor (PET) device, the PET device, and a semiconductor including the PET device are described. The method includes forming a first metal layer, forming a layer of a piezoelectric (PE) element on the first metal layer, and forming a second metal layer on the PE element. The method also includes forming a well above the second metal layer, forming a piezoresistive (PR) material in the well and above the well, and forming a passivation layer and a top metal layer above the PR material at the diameter of the PR material above the well, wherein a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer is a T-shaped structure. The method further includes forming a metal clamp layer as a top layer of the PET device.

Abstract translation: 描述了形成压电晶体管（PET）器件，PET器件和包括PET器件的半导体的方法。 该方法包括形成第一金属层，在第一金属层上形成压电（PE）元件层，以及在PE元件上形成第二金属层。 该方法还包括在第二金属层上方形成一个阱，在阱中和孔之上形成压阻（PR）材料，以及在PR材料上方的PR材料的上方形成钝化层和顶部金属层 井，其中井的截面形状，井上的PR材料，钝化层和顶部金属层是T形结构。 该方法还包括形成作为PET装置的顶层的金属夹持层。

公开(公告)号：US20160064641A1

公开(公告)日：2016-03-03

申请号：US14468822

申请日：2014-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce G. Elmegreen ,  Glenn J. Martyna ,  Dennis M. Newns

IPC: H01L41/083 ,  H01L41/047 ,  H01L41/18

CPC classification number: H01L41/107 ,  H01L41/047 ,  H01L41/0472 ,  H01L41/083 ,  H01L41/183 ,  H01L41/1876 ,  H01L49/00

Abstract: A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.