公开(公告)号：US07354848B2

公开(公告)日：2008-04-08

申请号：US11420940

申请日：2006-05-30

申请人： Ajit Paranjpe ,  Kangzhan Zhang

发明人： Ajit Paranjpe ,  Kangzhan Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L21/28044 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28282 ,  H01L21/823828 ,  H01L29/4925 ,  H01L29/513

摘要： A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin α-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second α-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.

摘要翻译： 已经描述了与常规CMOS栅极堆叠相比增加反转电容的CMOS栅极堆叠。 使用多晶硅栅极，代替栅极电介质层附近的常规多晶硅栅极，增加了可被激活的注入掺杂剂的量。 这种增加克服了限制常规CMOS栅极堆叠中的反相电容的多晶硅耗尽问题。 为了将多晶硅层整合到栅极堆叠中，在栅极介电层和多晶硅层之间沉积薄的α-Si层。 为了确保适当的自对准硅化物形成，多晶硅层被覆盖在多晶硅层上。 为了获得多晶SiGe上的细晶粒多晶硅，在多晶硅层和多晶硅层之间沉积第二个α-Si层。

公开(公告)号：US20070082507A1

公开(公告)日：2007-04-12

申请号：US11245373

申请日：2005-10-06

申请人： R. Iyer ,  Jacob Smith ,  Sean Seutter ,  Kangzhan Zhang ,  Alexander Tam ,  Kevin Cunningham ,  Phani Ramachandran

发明人： R. Iyer ,  Jacob Smith ,  Sean Seutter ,  Kangzhan Zhang ,  Alexander Tam ,  Kevin Cunningham ,  Phani Ramachandran

IPC分类号： H01L21/00

CPC分类号： C23C16/45565 ,  C23C16/345 ,  C23C16/4412 ,  C23C16/4557

摘要： A method and apparatus for low temperature deposition of doped silicon nitride films is disclosed. The improvements include a mechanical design for a CVD chamber that provides uniform heat distribution for low temperature processing and uniform distribution of process chemicals, and methods for depositing at least one layer comprising silicon and nitrogen on a substrate by heating a substrate, flowing a silicon containing precursor into a processing chamber having a mixing region defined by an adaptor ring and one or more blocker plates and an exhaust system heating the adapter ring and a portion of the exhaust system, flowing one or more of a hydrogen, germanium, boron, or carbon containing precursor into the processing chamber, and optionally flowing a nitrogen containing precursor into the processing chamber.

摘要翻译： 公开了一种用于低温沉积掺杂氮化硅膜的方法和装置。 这些改进包括用于CVD室的机械设计，其提供用于低温处理的均匀热分布和工艺化学品的均匀分布，以及用于通过加热衬底在衬底上沉积包含硅和氮的至少一层的方法，使含硅 前体进入具有由适配环和一个或多个阻断板限定的混合区域的处理室，以及加热接合环和排气系统的一部分，排出氢，锗，硼或碳的一部分的排气系统 并且可选地将含氮前体流入处理室。

公开(公告)号：US20060060920A1

公开(公告)日：2006-03-23

申请号：US10943424

申请日：2004-09-17

申请人： Ajit Paranjpe ,  Kangzhan Zhang

发明人： Ajit Paranjpe ,  Kangzhan Zhang

IPC分类号： H01L27/12 ,  H01L21/20

CPC分类号： H01L21/28044 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823828 ,  H01L29/40117 ,  H01L29/4925 ,  H01L29/513

摘要： A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin α-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second α-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.

摘要翻译： 已经描述了与常规CMOS栅极堆叠相比增加反转电容的CMOS栅极堆叠。 使用多晶硅栅极，代替栅极电介质层附近的常规多晶硅栅极，增加了可被激活的注入掺杂剂的量。 这种增加克服了限制常规CMOS栅极堆叠中的反相电容的多晶硅耗尽问题。 为了将多晶硅层整合到栅极堆叠中，在栅极介电层和多晶硅层之间沉积薄的α-Si层。 为了确保适当的自对准硅化物形成，多晶硅层被覆盖在多晶硅层上。 为了获得多晶SiGe上的细晶粒多晶硅，在多晶硅层和多晶硅层之间沉积第二个α-Si层。

公开(公告)号：US07465669B2

公开(公告)日：2008-12-16

申请号：US11273380

申请日：2005-11-12

申请人： R. Suryanarayanan Iyer ,  Sanjeev Tandon ,  Kangzhan Zhang ,  Rubi Lapena ,  Yuji Maeda

发明人： R. Suryanarayanan Iyer ,  Sanjeev Tandon ,  Kangzhan Zhang ,  Rubi Lapena ,  Yuji Maeda

IPC分类号： H01L21/311

CPC分类号： H01L21/3081 ,  C23C16/345 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/3185

摘要： Embodiments of methods for fabricating a silicon nitride stack on a semiconductor substrate are provided herein. In one embodiment, a method for fabricating a silicon nitride stack on a semiconductor substrate includes depositing a base layer including silicon nitride on the substrate using a first set of process conditions that selectively control the stress of the base layer; and depositing an upper layer including silicon nitride using a second set of process conditions that selectively control at least one of an oxidation resistance and a refractive index of the upper layer.

摘要翻译： 本文提供了在半导体衬底上制造氮化硅叠层的方法的实施例。 在一个实施例中，在半导体衬底上制造氮化硅叠层的方法包括：使用选择性地控制所述基底层的应力的第一组工艺条件，将包括氮化硅的基底层沉积在所述衬底上; 以及使用选择性地控制上层的抗氧化性和折射率中的至少一种的第二组工艺条件沉积包括氮化硅的上层。

公开(公告)号：US20070111538A1

公开(公告)日：2007-05-17

申请号：US11273380

申请日：2005-11-12

申请人： R. Iyer ,  Sanjeev Tandon ,  Kangzhan Zhang ,  Rubi Lapena ,  Yuji Maeda

发明人： R. Iyer ,  Sanjeev Tandon ,  Kangzhan Zhang ,  Rubi Lapena ,  Yuji Maeda

IPC分类号： H01L21/31

CPC分类号： H01L21/3081 ,  C23C16/345 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/3185

摘要： Embodiments of methods for fabricating a silicon nitride stack on a semiconductor substrate are provided herein. In one embodiment, a method for fabricating a silicon nitride stack on a semiconductor substrate includes depositing a base layer comprising silicon nitride on the substrate using a first set of process conditions that selectively control the stress of the base layer; and depositing an upper layer comprising silicon nitride using a second set of process conditions that selectively control at least one of an oxidation resistance and a refractive index of the upper layer.

摘要翻译： 本文提供了在半导体衬底上制造氮化硅叠层的方法的实施例。 在一个实施例中，在半导体衬底上制造氮化硅堆叠的方法包括：使用选择性地控制基底层的应力的第一组工艺条件，在衬底上沉积包括氮化硅的基底层; 以及使用选择性地控制上层的抗氧化性和折射率中的至少一种的第二组工艺条件沉积包括氮化硅的上层。

公开(公告)号：US20060084283A1

公开(公告)日：2006-04-20

申请号：US10970317

申请日：2004-10-20

申请人： Ajit Paranjpe ,  Kangzhan Zhang ,  Brendan McDougall ,  Wayne Vereb ,  Michael Patten ,  Alan Goldman ,  Somnath Nag

发明人： Ajit Paranjpe ,  Kangzhan Zhang ,  Brendan McDougall ,  Wayne Vereb ,  Michael Patten ,  Alan Goldman ,  Somnath Nag

IPC分类号： H01L21/31

CPC分类号： H01L21/0217 ,  C23C16/345 ,  C23C16/4412 ,  C23C16/45525 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/3185

摘要： A silicon nitride layer is deposited on a substrate within a processing region by introducing a silicon containing precursor into the processing region, exhausting gases in the processing region including the silicon containing precursor while uniformly, gradually reducing a pressure of the processing region, introducing a nitrogen containing precursor into the processing region, and exhausting gases in the processing region including the nitrogen containing precursor while uniformly, gradually reducing a pressure of the processing region. During the steps of exhausting, the slope of the pressure decrease with respect to time is substantially constant.

摘要翻译： 通过将含硅前体引入加工区域，在均匀地引入包含含硅前体的处理区域中的气体中逐渐降低加工区域的压力，引入氮气，在处理区域内的基板上沉积氮化硅层 并且在均匀地排出包含含氮前体的处理区域中的气体，逐渐降低加工区域的压力。 在排气步骤中，压力相对于时间的斜率减小是基本恒定的。

公开(公告)号：US20080145536A1

公开(公告)日：2008-06-19

申请号：US11610424

申请日：2006-12-13

申请人： KANGZHAN ZHANG ,  Sean M. Seutter ,  Jacob Grayson ,  R. Suryanarayanan Iyer

发明人： KANGZHAN ZHANG ,  Sean M. Seutter ,  Jacob Grayson ,  R. Suryanarayanan Iyer

IPC分类号： C23C16/00

CPC分类号： C23C16/34 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31111 ,  H01L21/318 ,  H01L29/4966 ,  H01L29/6659

摘要： A method and apparatus for depositing silicon boron nitride films is provided. The apparatus comprises a chamber, a gas mixing block connected to the chamber, and separate boron-containing precursor, silicon-containing precursor, and nitrogen-containing precursor gas line systems that are connected to the gas mixing block. Methods of depositing a silicon boron nitride film in the apparatus are provided. In another aspect, a method of depositing a silicon boron nitride film includes reacting a boron-containing precursor, silicon-containing precursor, and nitrogen-containing precursor in a chamber, wherein a ratio of the flow rate of the nitrogen-containing precursor into the chamber to the flow rate of the boron-containing precursor is greater than or equal to about 10.

摘要翻译： 提供了一种用于沉积硅氮化硼膜的方法和装置。 所述装置包括连接到所述室的室，气体混合块和连接到所述气体混合块的分离的含硼前体，含硅前体和含氮前体气体管线系统。 提供了在该装置中沉积硅氮化硼膜的方法。 在另一方面，沉积硅氮化硼膜的方法包括在室中使含硼前体，含硅前体和含氮前体反应，其中含氮前体的流速与 所述含硼前体的流速大于或等于约10。

公开(公告)号：US20060231925A1

公开(公告)日：2006-10-19

申请号：US11420940

申请日：2006-05-30

申请人： Ajit Paranjpe ,  Kangzhan Zhang

发明人： Ajit Paranjpe ,  Kangzhan Zhang

IPC分类号： H01L27/082

CPC分类号： H01L21/28044 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28282 ,  H01L21/823828 ,  H01L29/4925 ,  H01L29/513

摘要： A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin α-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second α-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.

摘要翻译： 已经描述了与常规CMOS栅极堆叠相比增加反转电容的CMOS栅极堆叠。 使用多晶硅栅极，代替栅极电介质层附近的常规多晶硅栅极，增加了可被激活的注入掺杂剂的量。 这种增加克服了限制常规CMOS栅极堆叠中的反相电容的多晶硅耗尽问题。 为了将多晶硅层整合到栅极堆叠中，在栅极介电层和多晶硅层之间沉积薄的α-Si层。 为了确保适当的自对准硅化物形成，多晶硅层被覆盖在多晶硅层上。 为了获得多晶SiGe上的细晶粒多晶硅，在多晶硅层和多晶硅层之间沉积第二个α-Si层。