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1.发明申请公开(公告)号：US20170109294A1
公开(公告)日：2017-04-20
申请号：US15394493
申请日：2016-12-29
申请人： ELIEZER WEISSMANN , KARTHIKEYAN KARTHIK VAITHIANATHAN , YOAV ZACH , BORIS GINZBURG , RONNY RONEN
发明人： ELIEZER WEISSMANN , KARTHIKEYAN KARTHIK VAITHIANATHAN , YOAV ZACH , BORIS GINZBURG , RONNY RONEN
IPC分类号： G06F12/1045 , G06F12/084 , G06F12/1081 , G06F12/1009 , G06F12/1072 , G06F12/0811 , G06F12/0875
CPC分类号： G06F9/3851 , G06F3/0646 , G06F3/0662 , G06F3/0668 , G06F9/3881 , G06F9/3887 , G06F12/0292 , G06F12/0811 , G06F12/084 , G06F12/0875 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F12/1072 , G06F12/1081 , G06F12/1441 , G06F12/145 , G06F2212/1024 , G06F2212/283 , G06F2212/302 , G06F2212/452 , G06F2212/60 , G06F2212/62 , G06F2212/65 , G06F2212/68 , G06F2212/683 , G06F2212/684
摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
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2.发明授权Apparatus and method for accelerating operations in a processor which uses shared virtual memory 有权用于在使用共享虚拟存储器的处理器中加速操作的装置和方法公开(公告)号：US09405701B2
公开(公告)日：2016-08-02
申请号：US13994577
申请日：2012-03-30
申请人： Eliezer Weissmann , Karthikeyan Karthik Vaithianathan , Yoav Zach , Boris Ginzburg , Ronny Ronen
发明人： Eliezer Weissmann , Karthikeyan Karthik Vaithianathan , Yoav Zach , Boris Ginzburg , Ronny Ronen
CPC分类号： G06F12/0811 , G06F3/0646 , G06F3/0662 , G06F3/0668 , G06F9/3851 , G06F9/3881 , G06F9/3887 , G06F12/0292 , G06F12/084 , G06F12/0875 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F12/1072 , G06F12/1081 , G06F12/1441 , G06F12/145 , G06F2212/1024 , G06F2212/283 , G06F2212/302 , G06F2212/452 , G06F2212/60 , G06F2212/62 , G06F2212/65 , G06F2212/68 , G06F2212/683 , G06F2212/684
摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
摘要翻译： 描述了用于将前端芯件耦合到加速器部件（例如，诸如图形加速器）的装置和方法。 例如，描述了一种装置，包括：加速器，包括执行指定的一组指令的一个或多个执行单元（EU） 和包括通信地耦合到加速器并且向加速器提供存储器访问服务的翻译后备缓冲器（TLB）的前端核心，所述存储器访问服务包括执行TLB查找操作以代表加速器映射虚拟到物理地址并作为响应 到需要访问系统存储器的加速器。
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3.发明申请公开(公告)号：US20160335090A1
公开(公告)日：2016-11-17
申请号：US15221557
申请日：2016-07-27
申请人： ELIEZER WEISSMANN , KARTHIKEYAN KARTHIK VAITHIANATHAN , YOAV ZACH , BORIS GINZBURG , RONNY RONEN
发明人： ELIEZER WEISSMANN , KARTHIKEYAN KARTHIK VAITHIANATHAN , YOAV ZACH , BORIS GINZBURG , RONNY RONEN
IPC分类号： G06F9/38 , G06F12/1027 , G06F12/0875
CPC分类号： G06F12/0811 , G06F3/0646 , G06F3/0662 , G06F3/0668 , G06F9/3851 , G06F9/3881 , G06F9/3887 , G06F12/0292 , G06F12/084 , G06F12/0875 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F12/1072 , G06F12/1081 , G06F12/1441 , G06F12/145 , G06F2212/1024 , G06F2212/283 , G06F2212/302 , G06F2212/452 , G06F2212/60 , G06F2212/62 , G06F2212/65 , G06F2212/68 , G06F2212/683 , G06F2212/684
摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
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4.发明申请CONTEXT SWITCHING MECHANISM FOR A PROCESSING CORE HAVING A GENERAL PURPOSE CPU CORE AND A TIGHTLY COUPLED ACCELERATOR 有权具有一般用途CPU核心的加工核心和紧密耦合加速器的上下文切换机制公开(公告)号：US20140344815A1
公开(公告)日：2014-11-20
申请号：US13993273
申请日：2012-03-30
申请人： Boris Ginzburg , Ronny Ronen , Eliezer Weissmann , Karthikeyan Karthik Vaithianathan , Ehud Cohen
发明人： Boris Ginzburg , Ronny Ronen , Eliezer Weissmann , Karthikeyan Karthik Vaithianathan , Ehud Cohen
IPC分类号： G06F9/48
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3851 , G06F9/3881 , G06F9/461 , G06F9/485
摘要： An apparatus is described having multiple cores, each core having: a) an accelerator; and, b) a general purpose CPU coupled to the accelerator. The general purpose CPU has functional unit logic circuitry to execute an instruction that returns an amount of storage space to store context information of the accelerator.
摘要翻译： 描述了具有多个芯的装置，每个芯具有：a）加速器; 和b）耦合到加速器的通用CPU。 通用CPU具有功能单元逻辑电路，以执行返回一定量的存储空间以存储加速器的上下文信息的指令。
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5.发明申请APPARATUS AND METHOD FOR ACCELERATING OPERATIONS IN A PROCESSOR WHICH USES SHARED VIRTUAL MEMORY 有权在使用共享虚拟内存的处理器中加速操作的装置和方法公开(公告)号：US20130318323A1
公开(公告)日：2013-11-28
申请号：US13994577
申请日：2012-03-30
申请人： Eliezer Weissmann , Karthikeyan Karthik Vaithianathan , Yoav Zach , Boris Ginzburg , Ronny Ronen
发明人： Eliezer Weissmann , Karthikeyan Karthik Vaithianathan , Yoav Zach , Boris Ginzburg , Ronny Ronen
IPC分类号： G06F12/10
CPC分类号： G06F12/0811 , G06F3/0646 , G06F3/0662 , G06F3/0668 , G06F9/3851 , G06F9/3881 , G06F9/3887 , G06F12/0292 , G06F12/084 , G06F12/0875 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F12/1072 , G06F12/1081 , G06F12/1441 , G06F12/145 , G06F2212/1024 , G06F2212/283 , G06F2212/302 , G06F2212/452 , G06F2212/60 , G06F2212/62 , G06F2212/65 , G06F2212/68 , G06F2212/683 , G06F2212/684
摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
摘要翻译： 描述了用于将前端芯件耦合到加速器部件（例如，诸如图形加速器）的装置和方法。 例如，描述了一种装置，包括：加速器，包括执行指定的一组指令的一个或多个执行单元（EU） 和包括通信地耦合到加速器并且向加速器提供存储器访问服务的翻译后备缓冲器（TLB）的前端核心，所述存储器访问服务包括执行TLB查找操作以代表加速器映射虚拟到物理地址并作为响应 到需要访问系统存储器的加速器。
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6.发明申请公开(公告)号：US20170153984A1
公开(公告)日：2017-06-01
申请号：US15394458
申请日：2016-12-29
申请人： ELIEZER WEISSMANN , KARTHIKEYAN KARTHIK VAITHIANATHAN , YOAV ZACH , BORIS GINZBURG , RONNY RONEN
发明人： ELIEZER WEISSMANN , KARTHIKEYAN KARTHIK VAITHIANATHAN , YOAV ZACH , BORIS GINZBURG , RONNY RONEN
IPC分类号： G06F12/1027 , G06F12/1009
CPC分类号： G06F9/3851 , G06F3/0646 , G06F3/0662 , G06F3/0668 , G06F9/3881 , G06F9/3887 , G06F12/0292 , G06F12/0811 , G06F12/084 , G06F12/0875 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F12/1072 , G06F12/1081 , G06F12/1441 , G06F12/145 , G06F2212/1024 , G06F2212/283 , G06F2212/302 , G06F2212/452 , G06F2212/60 , G06F2212/62 , G06F2212/65 , G06F2212/68 , G06F2212/683 , G06F2212/684
摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
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7.发明申请公开(公告)号：US20170109281A1
公开(公告)日：2017-04-20
申请号：US15394539
申请日：2016-12-29
申请人： ELIEZER WEISSMANN , KARTHIKEYAN KARTHIK VAITHIANATHAN , YOAV ZACH , BORIS GINZBURG , RONNY RONEN
发明人： ELIEZER WEISSMANN , KARTHIKEYAN KARTHIK VAITHIANATHAN , YOAV ZACH , BORIS GINZBURG , RONNY RONEN
IPC分类号： G06F12/0811 , G06F12/1009 , G06F12/1027
CPC分类号： G06F12/0811 , G06F3/0646 , G06F3/0662 , G06F3/0668 , G06F9/3851 , G06F9/3881 , G06F9/3887 , G06F12/0292 , G06F12/084 , G06F12/0875 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F12/1072 , G06F12/1081 , G06F12/1441 , G06F12/145 , G06F2212/1024 , G06F2212/283 , G06F2212/302 , G06F2212/452 , G06F2212/60 , G06F2212/62 , G06F2212/65 , G06F2212/68 , G06F2212/683 , G06F2212/684
摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
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