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112 条记录 (耗时 0.025 秒)

    Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform
    2.
    发明授权
    Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform 有权
    动态固定异构计算平台的不同类型处理器之间共享的虚拟页面

    公开(公告)号：US09164923B2

    公开(公告)日：2015-10-20

    申请号：US13175489

    申请日：2011-07-01

    申请人： Gad Sheaffer ,  Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann

    发明人： Gad Sheaffer ,  Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann

    IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/12

    CPC分类号： G06F12/1027 ,  G06F12/0804 ,  G06F12/126 ,  G06F13/1663 ,  G06F2212/303 ,  G06F2212/657 ,  G06F2212/684

    摘要： A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device (e.g., a graphics processing unit, GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. In one embodiment, the device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.

    摘要翻译： 计算机系统可以支持一种或多种技术来允许由非CPU设备（例如，图形处理单元，GPU）访问的存储器页的动态固定。 非CPU可以支持虚拟到物理地址映射，并且因此可以知道可能不被固定但可被非CPU访问的存储器页。 非CPU可以向诸如与CPU相关联的设备驱动程序的运行时组件通知或发送这样的信息。 在一个实施例中，设备驱动程序可以动态地执行可由非CPU访问的这种存储器页的钉扎。 设备驱动程序甚至可以取消内存页，这可能不再被非CPU访问。 这样的方法可以允许非CPU可以不再访问的存储器页面可用于分配给其他CPU和/或非CPU。

    Instruction segment recording scheme
    6.
    发明授权
    Instruction segment recording scheme 失效
    指令段记录方案

    公开(公告)号：US07757065B1

    公开(公告)日：2010-07-13

    申请号：US09708722

    申请日：2000-11-09

    申请人： Stephan J. Jourdan ,  Ronny Ronen ,  Lihu Rappoport

    发明人： Stephan J. Jourdan ,  Ronny Ronen ,  Lihu Rappoport

    IPC分类号： G06F9/30

    CPC分类号： G06F12/0875 ,  G06F9/3808

    摘要： In a front-end system for a processor, a recording scheme for instruction segments stores the instructions in reverse program order. Instruction segments may be traces, extended blocks or basic blocks. By storing the instructions in reverse program order, the instruction segment is easily extended to include additional instructions. The instruction segments may be extended without having to re-index tag arrays, pointers that associate instruction segments with other instruction segments.

    摘要翻译： 在用于处理器的前端系统中，用于指令段的记录方案以反向程序顺序存储指令。 指令段可以是跟踪，扩展块或基本块。 通过以反向程序顺序存储指令，指令段可以容易地扩展到包括附加指令。 指令段可以被扩展，而不必重新索引标签数组，将指令段与其他指令段相关联的指针。

    Low-power processor hint, such as from a pause instruction
    9.
    发明授权
    Low-power processor hint, such as from a pause instruction 有权
    低功耗处理器提示，例如从暂停指令

    公开(公告)号：US07159133B2

    公开(公告)日：2007-01-02

    申请号：US10759455

    申请日：2004-01-16

    申请人： Doron Orenstien ,  Ronny Ronen

    发明人： Doron Orenstien ,  Ronny Ronen

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/30083 ,  G06F9/3009 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3851 ,  Y02D10/126 ,  Y02D10/172

    摘要： A system and corresponding method use a PAUSE instruction as a low power hint in a single threaded or multithreaded environment using “processor slow mode.” One embodiment actually lowers the frequency of the processor clock. Another embodiment virtually lowers the frequency of the processor clock by gating M clock cycles out of every N clock cycles. When all threads have issued a PAUSE instruction, the processor enters slow mode and remains there for a while. After this while, the processor returns to normal mode. Alternatively, an event, such as an interrupt or an exception, can cause the processor to return to normal mode from slow mode.

    摘要翻译： 系统和相应的方法使用“处理器慢速模式”在单个线程或多线程环境中使用PAUSE指令作为低功耗提示。 一个实施例实际上降低了处理器时钟的频率。 另外一个实施例通过在N个时钟周期内门控M个时钟周期来实际上降低处理器时钟的频率。 当所有线程发出PAUSE指令时，处理器进入慢速模式并保持一段时间。 此后，处理器返回正常模式。 或者，诸如中断或异常的事件可以使处理器从慢速模式返回正常模式。