公开(公告)号：US20120080744A1

公开(公告)日：2012-04-05

申请号：US13308028

申请日：2011-11-30

申请人： Kazunari HATADE ,  Yoshiaki Hisamoto

发明人： Kazunari HATADE ,  Yoshiaki Hisamoto

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813

摘要： A semiconductor device has a semiconductor substrate having an upper main surface and a lower main surface. The semiconductor substrate includes a drain layer, a main base region, an underpad base region and a source region. The semiconductor device includes a first main electrode connected to the main base regions and the source region and not connected to the underpad base region, a gate electrode opposed to a channel region in the main base region interposed between the drain layer and the source region with a gate insulating film provided therebetween, a conductive gate pad opposed to an exposed surface of the underpad base region in the upper main surface with an insulating layer interposed therebetween and the conductive gate pad is connected to the gate electrode, and a second main electrode connected to the lower main surface.

摘要翻译： 半导体器件具有具有上主表面和下主表面的半导体衬底。 半导体衬底包括漏极层，主要基底区域，底部基底区域和源极区域。 半导体器件包括与主基极区域和源极区域连接并且不连接到底部基极区域的第一主电极，与漏极层和源极区域之间插入的主基极区域中的沟道区域相对的栅电极，其中， 设置在其间的栅绝缘膜，与上主表面中的下基板区域的暴露表面相对的导电栅极焊盘，绝缘层插入其间，导电栅极焊盘连接到栅电极，第二主电极连接 到下主表面。

公开(公告)号：US08008746B2

公开(公告)日：2011-08-30

申请号：US13016164

申请日：2011-01-28

申请人： Kazunari Hatade

发明人： Kazunari Hatade

IPC分类号： H01L29/739

CPC分类号： H01L29/7393 ,  H01L29/0696 ,  H01L29/0834

摘要： An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.

摘要翻译： 布置在发射电极下方的n +发射层由以预定间隔布置的凸部和与凸部相连的主体形成。 凸起部分区域与发射极电极接触，并且比p基极层更重掺杂的p +层至少布置在发射极层的下方。 在横向结构的功率晶体管中，可以提高寄生晶闸管的闩锁抗扰性，并且可以减少关断时间。

公开(公告)号：US07902634B2

公开(公告)日：2011-03-08

申请号：US12778611

申请日：2010-05-12

申请人： Kazunari Hatade

发明人： Kazunari Hatade

IPC分类号： H01L29/739

CPC分类号： H01L29/7393 ,  H01L29/0696 ,  H01L29/0834

摘要： An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.

公开(公告)号：US20070114614A1

公开(公告)日：2007-05-24

申请号：US11623806

申请日：2007-01-17

申请人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

发明人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

IPC分类号： H01L29/94 ,  H01L23/58

CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).

摘要翻译： 提供一种半导体器件，其能够避免由高压侧浮动偏置电压（VS）的负变化引起的故障和闭锁故障。 在n型杂质区（28）的上表面中，在NMOS（14）和PMOS（15）之间形成有与p型杂质区（33）接触的p + p型井（29）。 电极（41）位于p + +型杂质区域（33）上，电极（41）连接到高电压侧浮置偏移电压（VS）。 p型+杂质区域（33）的杂质浓度比p型阱（29）高，比p型阱（29）浅。 在p + + / - 型杂质区域（33）和PMOS（15）之间，形成n + +型杂质区域（32）的上表面 n型杂质区（28）。 电极（40）位于n + + +型杂质区（32）上，电极（40）连接到高压侧浮动电源绝对电压（VB）。

公开(公告)号：US20060011960A1

公开(公告)日：2006-01-19

申请号：US11229724

申请日：2005-09-20

申请人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

发明人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

IPC分类号： H01L29/94

CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).

摘要翻译： 提供一种半导体器件，其能够避免由高压侧浮动偏置电压（VS）的负变化引起的故障和闭锁故障。 在n型杂质区（28）的上表面中，在NMOS（14）和PMOS（15）之间形成有与p型杂质区（33）接触的p + p型井（29）。 电极（41）位于p + +型杂质区域（33）上，电极（41）连接到高电压侧浮置偏移电压（VS）。 p型+杂质区域（33）的杂质浓度比p型阱（29）高，比p型阱（29）浅。 在p + + / - 型杂质区域（33）和PMOS（15）之间，形成n + +型杂质区域（32）的上表面 n型杂质区（28）。 电极（40）位于n + + +型杂质区（32）上，电极（40）连接到高压侧浮动电源绝对电压（VB）。

公开(公告)号：US20130248926A1

公开(公告)日：2013-09-26

申请号：US13789012

申请日：2013-03-07

申请人： Kazunari HATADE

发明人： Kazunari HATADE

IPC分类号： H01L29/739 ,  H01L27/088

CPC分类号： H01L29/7393 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/7394

摘要： A horizontal semiconductor device having multiple unit semiconductor elements, each of said unit semiconductor element formed by an IGBT including: a semiconductor substrate of a first conductivity type; a semiconductor region of a second conductivity type formed on the semiconductor substrate; a collector layer of the first conductivity type formed within the semiconductor region; a ring-shaped base layer of the first conductivity type formed within the semiconductor region such that the base layer is off said collector layer but surrounds said collector layer; and a ring-shaped first emitter layer of the second conductivity type formed in said base layer, wherein movement of carriers between the first emitter layer and the collector layer is controlled in a channel region formed in the base layer, and the unit semiconductor elements are disposed adjacent to each other.

摘要翻译： 一种具有多个单位半导体元件的水平半导体器件，由IGBT形成的每个所述单位半导体元件包括：第一导电类型的半导体衬底; 形成在半导体衬底上的第二导电类型的半导体区域; 形成在半导体区域内的第一导电类型的集电极层; 形成在半导体区域内的第一导电类型的环形基底层，使得基底层离开所述集电极层但围绕所述集电极层; 以及形成在所述基底层中的第二导电类型的环形的第一发射极层，其中在所述第一发射极层和所述集电极层之间的载流子的移动被控制在形成在所述基极层中的沟道区域中，并且所述单位半导体元件 彼此相邻放置。

公开(公告)号：US08183631B2

公开(公告)日：2012-05-22

申请号：US11612341

申请日：2006-12-18

申请人： Kazunari Hatade ,  Yoshiaki Hisamoto

发明人： Kazunari Hatade ,  Yoshiaki Hisamoto

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813

摘要： A semiconductor device has a semiconductor substrate having an upper main surface and a lower main surface. The semiconductor substrate includes a drain layer, a main base region, an underpad base region and a source region. The semiconductor device includes a first main electrode connected to the main base region and the source region and not connected to the underpad base region, a gate electrode opposed to a channel region in the main base region interposed between the drain layer and the source region with a gate insulating film provided therebetween, a conductive gate pad opposed to an exposed surface of the underpad base region in the upper main surface with an insulating layer interposed therebetween and the conductive gate pad is connected to the gate electrode, and a second main electrode connected to the lower main surface.

摘要翻译： 半导体器件具有具有上主表面和下主表面的半导体衬底。 半导体衬底包括漏极层，主要基底区域，底部基底区域和源极区域。 半导体器件包括连接到主基极区域和源极区域并且不连接到欠底部基极区域的第一主电极，与漏极层和源极区域之间插入的主基极区域中的沟道区域相对的栅电极， 设置在其间的栅绝缘膜，与上主表面中的下基板区域的暴露表面相对的导电栅极焊盘，绝缘层插入其间，导电栅极焊盘连接到栅电极，第二主电极连接 到下主表面。

公开(公告)号：US20110018028A1

公开(公告)日：2011-01-27

申请号：US12891842

申请日：2010-09-28

申请人： Kazunari HATADE

发明人： Kazunari HATADE

IPC分类号： H01L29/739

CPC分类号： H01L29/7393 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/7394

摘要： A horizontal semiconductor device having multiple unit semiconductor elements, each of said unit semiconductor element formed by an IGBT including: a semiconductor substrate of a first conductivity type; a semiconductor region of a second conductivity type formed on the semiconductor substrate; a collector layer of the first conductivity type formed within the semiconductor region; a ring-shaped base layer of the first conductivity type formed within the semiconductor region such that the base layer is off said collector layer but surrounds said collector layer; and a ring-shaped first emitter layer of the second conductivity type formed in said base layer, wherein movement of carriers between the first emitter layer and the collector layer is controlled in a channel region formed in the base layer, and the unit semiconductor elements are disposed adjacent to each other.

摘要翻译： 一种具有多个单位半导体元件的水平半导体器件，由IGBT形成的每个所述单位半导体元件包括：第一导电类型的半导体衬底; 形成在半导体衬底上的第二导电类型的半导体区域; 形成在半导体区域内的第一导电类型的集电极层; 形成在半导体区域内的第一导电类型的环形基底层，使得基底层离开所述集电极层但围绕所述集电极层; 以及形成在所述基底层中的第二导电类型的环形的第一发射极层，其中在所述第一发射极层和所述集电极层之间的载流子的移动被控制在形成在所述基极层中的沟道区域中，并且所述单位半导体元件 彼此相邻放置。

公开(公告)号：US20080265334A1

公开(公告)日：2008-10-30

申请号：US12164696

申请日：2008-06-30

申请人： Kazunari HATADE ,  Hajime AKIYAMA ,  Kazuhiro SHIMIZU

发明人： Kazunari HATADE ,  Hajime AKIYAMA ,  Kazuhiro SHIMIZU

IPC分类号： H01L27/092

CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).

公开(公告)号：US07190034B2

公开(公告)日：2007-03-13

申请号：US11229724

申请日：2005-09-20

申请人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

发明人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).

摘要翻译： 提供一种半导体器件，其能够避免由高压侧浮动偏置电压（VS）的负变化引起的故障和闭锁故障。 在n型杂质区（28）的上表面中，在NMOS（14）和PMOS（15）之间形成有与p型杂质区（33）接触的p + p型井（29）。 电极（41）位于p + +型杂质区域（33）上，电极（41）连接到高电压侧浮置偏移电压（VS）。 p型+杂质区域（33）的杂质浓度比p型阱（29）高，比p型阱（29）浅。 在p + + / - 型杂质区域（33）和PMOS（15）之间，形成n + +型杂质区域（32）的上表面 n型杂质区（28）。 电极（40）位于n + + +型杂质区（32）上，电极（40）连接到高压侧浮动电源绝对电压（VB）。