公开(公告)号：US08437426B2

公开(公告)日：2013-05-07

申请号：US12567856

申请日：2009-09-28

申请人： Hidetoshi Kawauchi ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Kazuhiro Shimizu ,  Kazuhisa Funamoto

发明人： Hidetoshi Kawauchi ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Kazuhiro Shimizu ,  Kazuhisa Funamoto

IPC分类号： H04B1/38 ,  H04N7/12 ,  H04L27/00

CPC分类号： H04L27/2662 ,  H04L25/0232 ,  H04L25/03159 ,  H04L27/2656 ,  H04L27/2665

摘要： Disclosed herein is a receiving apparatus including: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.

摘要翻译： 本发明公开了一种接收装置，包括：第一至第三位置确定部分，被配置为确定FFT间隔的起始位置，其作为由FFT部分进行FFT的信号间隔; 选择部，被配置为选择由所述第一至第三位置确定部确定的所述FFT间隔的那些起始位置之一; FFT部，被配置为通过将由选择部选择出的开始位置作为FFT间隔的开始位置，对OFDM时域信号进行FFT，以生成第一OFDM频域信号。

公开(公告)号：US08259494B2

公开(公告)日：2012-09-04

申请号：US12855507

申请日：2010-08-12

申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： G11C11/34

CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

公开(公告)号：US08045945B2

公开(公告)日：2011-10-25

申请号：US12393093

申请日：2009-02-26

申请人： Hidetoshi Kawauchi ,  Tadaaki Yuba ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Takuya Okamoto ,  Tamotsu Ikeda ,  Koji Naniwada ,  Kazuhiro Shimizu ,  Lachlan Bruce Michael

发明人： Hidetoshi Kawauchi ,  Tadaaki Yuba ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Takuya Okamoto ,  Tamotsu Ikeda ,  Koji Naniwada ,  Kazuhiro Shimizu ,  Lachlan Bruce Michael

IPC分类号： H04B1/10

CPC分类号： H04B1/1036 ,  H04L5/0048 ,  H04L25/0216 ,  H04L25/0232

摘要： A reception apparatus including an extraction section; a transmission line characteristic estimation section; an interpolation section; a compensation section; a detection section; and a selection section.

摘要翻译： 一种接收装置，包括提取部分; 传输线特性估计部; 插值部分; 赔偿部分; 检测部; 和选择部分。

公开(公告)号：US07977787B2

公开(公告)日：2011-07-12

申请号：US12332409

申请日：2008-12-11

申请人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

发明人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/67271 ,  H01L21/67282 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

摘要翻译： 半导体器件制造装置具备：具有喷射导电性溶剂的印刷头，绝缘性溶剂和界面处理液的图形印刷部。 打印头形成为使得可以基于来自晶片测试部件的绘图图案的信息，从存储部分获得关于晶片的信息和来自芯片坐标识别部分的坐标信息，将期望的电路图形图案印刷在晶片上 。 在根据本发明的半导体器件制造方法中，通过使用半导体器件制造设备以通过印刷处理形成期望的电路的方式制造半导体器件。 在半导体器件中，焊盘电极等以能够通过打印电路图形进行修整处理的方式形成。

公开(公告)号：US07786525B2

公开(公告)日：2010-08-31

申请号：US12104945

申请日：2008-04-17

申请人： Kazuhiro Shimizu

发明人： Kazuhiro Shimizu

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336

摘要： A nonvolatile semiconductor memory device includes an element isolation insulating film buried in first trenches, a floating gate electrode formed on an element forming region with a first gate insulating film being interposed between them, and a second gate insulating film formed on upper portions of the floating gate electrode and an element isolation insulating film. The floating gate electrode is formed so as to have a side that extends from a bottom thereof to its upper portion and is substantially an extension of a sidewall of each first trench. The element isolation insulating film includes a portion located between its sidewall and the sidewall of a second trench, and the portion of the element isolation insulating film having a film thickness in a direction along the upper surface of the semiconductor substrate. The film thickness is equal to a film thickness of the second gate insulating film.

摘要翻译： 非易失性半导体存储器件包括埋在第一沟槽中的元件隔离绝缘膜，形成在元件形成区域上的浮置栅极，第一栅极绝缘膜介于其间;以及第二栅极绝缘膜，形成在浮置的上部 栅电极和元件隔离绝缘膜。 浮栅电极形成为具有从其底部延伸到其上部并且基本上是每个第一沟槽的侧壁的延伸部的侧面。 元件隔离绝缘膜包括位于其侧壁和第二沟槽的侧壁之间的部分，元件隔离绝缘膜的沿着半导体衬底的上表面的方向具有膜厚度的部分。 膜厚度等于第二栅极绝缘膜的膜厚度。

公开(公告)号：US20090256234A1

公开(公告)日：2009-10-15

申请号：US12489841

申请日：2009-06-23

申请人： Kazuhiro SHIMIZU

发明人： Kazuhiro SHIMIZU

IPC分类号： H01L27/06

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is configured that a high-withstand voltage semiconductor device and logic circuits are integrated on a single chip and that a high-withstand voltage high-potential island including the high-potential-side logic circuit is separated using multiple partition walls enclosing therearound. The semiconductor device is provided with a multi-trench separation region having a level shift wire region that is used to connect the high-potential-side logic circuit to the high-potential-side electrode of the high-withstand voltage semiconductor device.

摘要翻译： 半导体器件被配置为将高耐压电压半导体器件和逻辑电路集成在单个芯片上，并且包括高电位侧逻辑电路的高耐压电压高电位岛被分离使用围绕其的多个分隔壁 。 半导体器件具有多沟槽分离区域，该多沟槽分离区域具有用于将高电位侧逻辑电路连接到高耐压半导体器件的高电位侧电极的电平移位线区域。

公开(公告)号：US20090053269A1

公开(公告)日：2009-02-26

申请号：US11887369

申请日：2006-09-07

申请人： Kazuhiro Shimizu

发明人： Kazuhiro Shimizu

IPC分类号： A61K8/89 ,  A61K8/72

CPC分类号： A61K8/891 ,  A61K8/02 ,  A61K8/022 ,  A61K8/0241 ,  A61K8/11 ,  A61K2800/262 ,  A61K2800/412 ,  A61K2800/622 ,  A61K2800/624 ,  A61K2800/654 ,  A61Q1/02 ,  A61Q1/08 ,  A61Q1/10 ,  A61Q1/12

摘要： The present invention provides a novel solid powder which has transparency in its appearance, and has excellent usability and, in addition, excellent feeling of use such as dry feeling and fresh light feeling without sticky feeling during application. It is achieved by a solid powder cosmetic comprising: (A) 25 to 55% by mass of elastic powder mixture; (B) 20 to 40% by mass of non-elastic spherical silicone resin powder with an average particle diameter within the range of 0.1 to 50 μm; and (C) 25 to 55% by mass of oil, as essential components, wherein (A) the elastic powder mixture comprises one or more types of each (A1) an elastic powder and (A2) a composite powder obtained by coating the periphery of an elastic powder with a non-elastic material, said solid powder cosmetic being obtained by caking a mixed composition of these essential components.

摘要翻译： 本发明提供了一种外观透明的新型固体粉末，其使用性优异，并且在使用时具有优良的使用感，如干燥感和新鲜感觉，无粘性。 其通过固体粉末化妆品实现，其包含：（A）25〜55质量％的弹性粉末混合物; （B）20〜40质量％的平均粒径为0.1〜50μm的非弹性球形的有机硅树脂粉末; 和（C）25〜55质量％的油作为必要成分，其中（A）弹性粉末混合物包含一种或多种（A1）弹性粉末和（A2）通过涂覆周边 具有非弹性材料的弹性粉末，所述固体粉末化妆品通过粘结这些基本组分的混合组合物而获得。

公开(公告)号：US20080265334A1

公开(公告)日：2008-10-30

申请号：US12164696

申请日：2008-06-30

申请人： Kazunari HATADE ,  Hajime AKIYAMA ,  Kazuhiro SHIMIZU

发明人： Kazunari HATADE ,  Hajime AKIYAMA ,  Kazuhiro SHIMIZU

IPC分类号： H01L27/092

CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).

公开(公告)号：US20080110018A1

公开(公告)日：2008-05-15

申请号：US11720711

申请日：2005-09-29

申请人： Kazuhiro Shimizu ,  Masanobu Yagi ,  Kenichiro Hanamura ,  Mitsuyuki Takayasu ,  Kiyoe Nagai ,  Tomoo Iijima

发明人： Kazuhiro Shimizu ,  Masanobu Yagi ,  Kenichiro Hanamura ,  Mitsuyuki Takayasu ,  Kiyoe Nagai ,  Tomoo Iijima

IPC分类号： H01R43/00 ,  H05K3/20

CPC分类号： H05K3/4038 ,  B32B37/26 ,  B32B2457/08 ,  H05K3/022 ,  H05K3/06 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1461 ,  Y10T29/49128 ,  Y10T29/49156 ,  Y10T29/49163

摘要： A process for manufacturing a multilayer wiring board including the steps of forming an insulating layer on a base provided with a bump for interlayer connection, bonding a copper foil onto the insulating layer by a thermocompression bonding by sandwiching the copper foil between stainless steel plates, and patterning the copper foil, in which a metal foil is interposed at least between each of the stainless plates and the copper foil at the time of the thermocompression bonding. At this time, a mold release layer is formed on a surface of the metal foil to be imposed. Thus, such a multilayer wiring board can be manufactured that prevents sticking of a product after molding (cementing of the copper foil) and excels in dimensional stability without occurrence of wrinkling and ruggedness.

摘要翻译： 一种多层布线板的制造方法，包括以下步骤：在设置有用于层间连接的凸块的基底上形成绝缘层，通过将铜箔夹在不锈钢板之间通过热压接将铜箔接合到绝缘层上;以及 在热压接时，至少在每个不锈钢板和铜箔之间插入金属箔的铜箔图案化。 此时，在要施加的金属箔的表面上形成脱模层。 因此，可以制造这样的多层布线板，其防止成型后的产品粘附（铜箔的粘合），并且尺寸稳定性优异，而不会发生起皱和粗糙。

公开(公告)号：US07294901B2

公开(公告)日：2007-11-13

申请号：US10761235

申请日：2004-01-22

申请人： Kazuhiro Shimizu

发明人： Kazuhiro Shimizu

IPC分类号： H01L23/58

CPC分类号： H01L29/7816 ,  H01L21/763 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/7801 ,  H01L29/7823 ,  H01L2924/0002 ,  H01L2924/00

摘要： A p impurity region (3) defines a RESURF isolation region in an n− semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n− semiconductor layer (2) in the RESURF isolation region. An nMOS transistor (103) is provided in the trench isolation region. A control circuit is provided in the RESURF isolation region excluding the trench isolation region. An n+ buried impurity region (4) is provided at the interface between the n− semiconductor layer (2) and a p− semiconductor substrate (1), and under an n+ impurity region 7 connected to a drain electrode (14) of the nMOS transistor (103).

摘要翻译： p杂质区（3）在n + - 半导体层（2）中限定了RESURF隔离区。 沟槽隔离结构（8a）和p杂质区（3）共同限定了RESURF隔离区中的n + - 半导体层（2）中的沟槽隔离区。 nMOS晶体管（103）设置在沟槽隔离区域中。 在除了沟槽隔离区域之外的RESURF隔离区域中提供控制电路。 在n + - 半导体层（2）和半导体衬底（2）之间的界面处设置有n + + / / 1），以及连接到nMOS晶体管（103）的漏电极（14）的n + H + +杂质区域7。