公开(公告)号：US08202740B2

公开(公告)日：2012-06-19

申请号：US12895649

申请日：2010-09-30

申请人： Kanya Hamada ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

发明人： Kanya Hamada ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

IPC分类号： H01L21/66 ,  H01L21/44

CPC分类号： H01L22/20 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318583 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SIP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.

摘要翻译： 提供了用于小型化的SiP或PoP的半导体器件，其制造方法以及适用于实现系统简化和提高其效率的SIP和PoP的测试方法。 对包括被确定为无缺陷的第一存储器电路和包括第二存储器电路的第二半导体器件和执行被确定为无缺陷的程序的信号处理的信号处理电路的第一半导体器件进行排序。 分类器件被组装为一体的半导体器件。 在用于测试的电路板上，提供与半导体器件的实际操作相当的时钟信号。 用于对第一存储器电路进行性能测试的测试程序从测试器写入第二半导体器件的第二存储器电路。 在信号处理电路中，根据与时钟信号对应的写入测试程序对第一存储器电路进行性能测试。 在该性能测试中，故障/无故障确定的结果被输出到测试器。

公开(公告)号：US20080303173A1

公开(公告)日：2008-12-11

申请号：US12127788

申请日：2008-05-27

申请人： Kanya HAMADA ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

发明人： Kanya HAMADA ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

IPC分类号： H01L21/66 ,  G01R31/26 ,  H01L23/52

CPC分类号： H01L22/20 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318583 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.

摘要翻译： 提供了用于小型化的SiP或PoP的半导体器件，其制造方法以及适用于实现系统的简化和提高效率的SiP和PoP的测试方法。 对包括被确定为无缺陷的第一存储器电路和包括第二存储器电路的第二半导体器件和执行被确定为无缺陷的程序的信号处理的信号处理电路的第一半导体器件进行排序。 分类器件被组装为一体的半导体器件。 在用于测试的电路板上，提供与半导体器件的实际操作相当的时钟信号。 用于对第一存储器电路进行性能测试的测试程序从测试器写入第二半导体器件的第二存储器电路。 在信号处理电路中，根据与时钟信号对应的写入测试程序对第一存储器电路进行性能测试。 在该性能测试中，故障/无故障确定的结果被输出到测试器。

公开(公告)号：US20110018573A1

公开(公告)日：2011-01-27

申请号：US12895649

申请日：2010-09-30

申请人： Kanya HAMADA ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

发明人： Kanya HAMADA ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

IPC分类号： G01R31/26

CPC分类号： H01L22/20 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318583 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SIP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.

摘要翻译： 提供了一种用于小型化的SiP或PoP的半导体器件，其制造方法以及适用于实现系统简化和提高其效率的SIP和PoP的测试方法。 对包括被确定为无缺陷的第一存储器电路和包括第二存储器电路的第二半导体器件和执行被确定为无缺陷的程序的信号处理的信号处理电路的第一半导体器件进行排序。 分类器件被组装为一体的半导体器件。 在用于测试的电路板上，提供与半导体器件的实际操作相当的时钟信号。 用于对第一存储器电路进行性能测试的测试程序从测试器写入第二半导体器件的第二存储器电路。 在信号处理电路中，根据与时钟信号对应的写入测试程序对第一存储器电路进行性能测试。 在该性能测试中，故障/无故障确定的结果被输出到测试器。

公开(公告)号：US07816154B2

公开(公告)日：2010-10-19

申请号：US12127788

申请日：2008-05-27

申请人： Kanya Hamada ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

发明人： Kanya Hamada ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

IPC分类号： H01L21/66 ,  H01L21/44

CPC分类号： H01L22/20 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318583 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.

摘要翻译： 提供了用于小型化的SiP或PoP的半导体器件，其制造方法以及适用于实现系统的简化和提高效率的SiP和PoP的测试方法。 对包括被确定为无缺陷的第一存储器电路和包括第二存储器电路的第二半导体器件和执行被确定为无缺陷的程序的信号处理的信号处理电路的第一半导体器件进行排序。 分类器件被组装为一体的半导体器件。 在用于测试的电路板上，提供与半导体器件的实际操作相当的时钟信号。 用于对第一存储器电路进行性能测试的测试程序从测试器写入第二半导体器件的第二存储器电路。 在信号处理电路中，根据与时钟信号对应的写入测试程序对第一存储器电路进行性能测试。 在该性能测试中，故障/无故障确定的结果被输出到测试器。