公开(公告)号：US08202740B2

公开(公告)日：2012-06-19

申请号：US12895649

申请日：2010-09-30

申请人： Kanya Hamada ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

发明人： Kanya Hamada ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

IPC分类号： H01L21/66 ,  H01L21/44

CPC分类号： H01L22/20 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318583 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SIP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.

摘要翻译： 提供了用于小型化的SiP或PoP的半导体器件，其制造方法以及适用于实现系统简化和提高其效率的SIP和PoP的测试方法。 对包括被确定为无缺陷的第一存储器电路和包括第二存储器电路的第二半导体器件和执行被确定为无缺陷的程序的信号处理的信号处理电路的第一半导体器件进行排序。 分类器件被组装为一体的半导体器件。 在用于测试的电路板上，提供与半导体器件的实际操作相当的时钟信号。 用于对第一存储器电路进行性能测试的测试程序从测试器写入第二半导体器件的第二存储器电路。 在信号处理电路中，根据与时钟信号对应的写入测试程序对第一存储器电路进行性能测试。 在该性能测试中，故障/无故障确定的结果被输出到测试器。

公开(公告)号：US20080303173A1

公开(公告)日：2008-12-11

申请号：US12127788

申请日：2008-05-27

申请人： Kanya HAMADA ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

发明人： Kanya HAMADA ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

IPC分类号： H01L21/66 ,  G01R31/26 ,  H01L23/52

CPC分类号： H01L22/20 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318583 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.

摘要翻译： 提供了用于小型化的SiP或PoP的半导体器件，其制造方法以及适用于实现系统的简化和提高效率的SiP和PoP的测试方法。 对包括被确定为无缺陷的第一存储器电路和包括第二存储器电路的第二半导体器件和执行被确定为无缺陷的程序的信号处理的信号处理电路的第一半导体器件进行排序。 分类器件被组装为一体的半导体器件。 在用于测试的电路板上，提供与半导体器件的实际操作相当的时钟信号。 用于对第一存储器电路进行性能测试的测试程序从测试器写入第二半导体器件的第二存储器电路。 在信号处理电路中，根据与时钟信号对应的写入测试程序对第一存储器电路进行性能测试。 在该性能测试中，故障/无故障确定的结果被输出到测试器。

公开(公告)号：US20110018573A1

公开(公告)日：2011-01-27

申请号：US12895649

申请日：2010-09-30

申请人： Kanya HAMADA ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

发明人： Kanya HAMADA ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

IPC分类号： G01R31/26

CPC分类号： H01L22/20 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318583 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SIP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.

摘要翻译： 提供了一种用于小型化的SiP或PoP的半导体器件，其制造方法以及适用于实现系统简化和提高其效率的SIP和PoP的测试方法。 对包括被确定为无缺陷的第一存储器电路和包括第二存储器电路的第二半导体器件和执行被确定为无缺陷的程序的信号处理的信号处理电路的第一半导体器件进行排序。 分类器件被组装为一体的半导体器件。 在用于测试的电路板上，提供与半导体器件的实际操作相当的时钟信号。 用于对第一存储器电路进行性能测试的测试程序从测试器写入第二半导体器件的第二存储器电路。 在信号处理电路中，根据与时钟信号对应的写入测试程序对第一存储器电路进行性能测试。 在该性能测试中，故障/无故障确定的结果被输出到测试器。

公开(公告)号：US07816154B2

公开(公告)日：2010-10-19

申请号：US12127788

申请日：2008-05-27

申请人： Kanya Hamada ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

发明人： Kanya Hamada ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

IPC分类号： H01L21/66 ,  H01L21/44

CPC分类号： H01L22/20 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318583 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.

摘要翻译： 提供了用于小型化的SiP或PoP的半导体器件，其制造方法以及适用于实现系统的简化和提高效率的SiP和PoP的测试方法。 对包括被确定为无缺陷的第一存储器电路和包括第二存储器电路的第二半导体器件和执行被确定为无缺陷的程序的信号处理的信号处理电路的第一半导体器件进行排序。 分类器件被组装为一体的半导体器件。 在用于测试的电路板上，提供与半导体器件的实际操作相当的时钟信号。 用于对第一存储器电路进行性能测试的测试程序从测试器写入第二半导体器件的第二存储器电路。 在信号处理电路中，根据与时钟信号对应的写入测试程序对第一存储器电路进行性能测试。 在该性能测试中，故障/无故障确定的结果被输出到测试器。

公开(公告)号：US06696849B2

公开(公告)日：2004-02-24

申请号：US09964708

申请日：2001-09-28

申请人： Naoto Ban ,  Masaaki Namba ,  Akio Hasebe ,  Yuji Wada ,  Ryuji Kohno ,  Akira Seito ,  Yasuhiro Motoyama

发明人： Naoto Ban ,  Masaaki Namba ,  Akio Hasebe ,  Yuji Wada ,  Ryuji Kohno ,  Akira Seito ,  Yasuhiro Motoyama

IPC分类号： G01R3102

CPC分类号： G01R31/2831

摘要： A testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these blocks and employs the wafer full surface simultaneous contact system of the divided contactor integration type. Each probe of the silicon contactor is equally placed in contact in the predetermined pressure with each test pad of each chip of the test wafer by mechanically pressuring each silicon contactor block which moves individually, the test control signal is supplied to each chip and this test result signal is obtained for the wafer level burn-in test.

摘要翻译： 一种半导体集成电路器件的测试装置和制造方法，用于通过在晶片级老化中放置与晶片的整个表面均匀接触的分割的接触器来降低制造成本，从而能够修复每个接触器并提高产量 的接触器。 测试装置中的机械加压系统的盒式结构由多个分开的硅接触器块和用于集成这些块的引导框架构成，并且采用分开的接触器一体化型的晶片全表面同时接触系统。 硅接触器的每个探针通过机械加压每个单独移动的硅接触器块，将测试控制信号提供给每个芯片，并且测试结果与测试晶片的每个芯片的每个测试焊盘等同地以预定压力接触 获得晶片级老化测试信号。

公开(公告)号：US07422914B2

公开(公告)日：2008-09-09

申请号：US11936358

申请日：2007-11-07

申请人： Yuji Wada ,  Akira Seito ,  Masaaki Namba

发明人： Yuji Wada ,  Akira Seito ,  Masaaki Namba

IPC分类号： G01R31/26

CPC分类号： G01R31/287 ,  G01R31/286 ,  G01R31/31718 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00

摘要： A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

摘要翻译： 在具有效率低成本的包括半导体存储器的半导体集成电路器件上进行存储器测试。 在测试老化系统中，24个测试板按时间顺序进行处理，测试板逐个循环。 在这种情况下，以单板处理的顺序进行存储器测试：测试开始于已经嵌入半导体集成电路器件的测试板，半导体集成电路器件被放电，从具有 经过测试

公开(公告)号：US07306957B2

公开(公告)日：2007-12-11

申请号：US11012225

申请日：2004-12-16

申请人： Yuji Wada ,  Akira Seito ,  Masaaki Namba

发明人： Yuji Wada ,  Akira Seito ,  Masaaki Namba

IPC分类号： G01R31/26

CPC分类号： G01R31/287 ,  G01R31/286 ,  G01R31/31718 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00

摘要： A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

摘要翻译： 在具有效率低成本的包括半导体存储器的半导体集成电路器件上进行存储器测试。 在测试老化系统中，24个测试板按时间顺序进行处理，测试板逐个循环。 在这种情况下，以单板处理的顺序进行存储器测试：测试开始于已经嵌入半导体集成电路器件的测试板，半导体集成电路器件被放电，从具有 经过测试

公开(公告)号：US20080293167A1

公开(公告)日：2008-11-27

申请号：US12184563

申请日：2008-08-01

申请人： Yuji Wada ,  Akira Seito ,  Masaaki Namba

发明人： Yuji Wada ,  Akira Seito ,  Masaaki Namba

IPC分类号： H01L21/66

CPC分类号： G01R31/287 ,  G01R31/286 ,  G01R31/31718 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00

摘要： A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

摘要翻译： 在具有效率低成本的包括半导体存储器的半导体集成电路器件上进行存储器测试。 在测试老化系统中，24个测试板按时间顺序进行处理，测试板逐个循环。 在这种情况下，以单板处理的顺序进行存储器测试：测试开始于已经嵌入半导体集成电路器件的测试板，半导体集成电路器件被放电，从具有 经过测试

公开(公告)号：US20080070330A1

公开(公告)日：2008-03-20

申请号：US11936358

申请日：2007-11-07

申请人： Yuji Wada ,  Akira Seito ,  Masaaki Namba

发明人： Yuji Wada ,  Akira Seito ,  Masaaki Namba

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G01R31/287 ,  G01R31/286 ,  G01R31/31718 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00

摘要： A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

公开(公告)号：US20050153465A1

公开(公告)日：2005-07-14

申请号：US11012225

申请日：2004-12-16

申请人： Yuji Wada ,  Akira Seito ,  Masaaki Namba

发明人： Yuji Wada ,  Akira Seito ,  Masaaki Namba

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C29/56 ,  H01L21/66

CPC分类号： G01R31/287 ,  G01R31/286 ,  G01R31/31718 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00

摘要： A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

摘要翻译： 在具有效率低成本的包括半导体存储器的半导体集成电路器件上进行存储器测试。 在测试老化系统中，24个测试板按时间顺序进行处理，测试板逐个循环。 在这种情况下，以单板处理的顺序进行存储器测试：测试开始于已经嵌入半导体集成电路器件的测试板，半导体集成电路器件被放电，从具有 经过测试