公开(公告)号：US08803974B2

公开(公告)日：2014-08-12

申请号：US13265410

申请日：2010-11-30

申请人： Yoshiaki Nakajima ,  Shinichi Shimoyama

发明人： Yoshiaki Nakajima ,  Shinichi Shimoyama

IPC分类号： H04N7/18

CPC分类号： G07F17/3288 ,  G06Q10/04 ,  G06Q10/06 ,  G06Q50/34 ,  G07F17/323

摘要： There are provided an information providing system, an information providing method and an information providing program capable of providing information for enabling conditions of a horse entered in a race to be rapidly confirmed.A system control unit 15 according to the present application acquires moving image data in which horses are captured, extracts a plurality of items of still image data of the horses from the acquired moving image data, generates a horse list displaying the horse names for which a link to acquire and display the still image data by a user terminal 3-k is set, and distributes it to the user terminal 3-k.

摘要翻译： 提供了能够提供信息的信息提供系统，信息提供方法和信息提供程序，能够快速确认在竞赛中输入的马的条件的信息。 根据本申请的系统控制单元15获取捕获马的运动图像数据，从所获取的运动图像数据中提取马的多个静止图像数据项目，生成马列表，其显示马名称 设置由用户终端3-k获取和显示静止图像数据的链接，并将其分发给用户终端3-k。

公开(公告)号：US08202740B2

公开(公告)日：2012-06-19

申请号：US12895649

申请日：2010-09-30

申请人： Kanya Hamada ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

发明人： Kanya Hamada ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

IPC分类号： H01L21/66 ,  H01L21/44

CPC分类号： H01L22/20 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318583 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SIP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.

摘要翻译： 提供了用于小型化的SiP或PoP的半导体器件，其制造方法以及适用于实现系统简化和提高其效率的SIP和PoP的测试方法。 对包括被确定为无缺陷的第一存储器电路和包括第二存储器电路的第二半导体器件和执行被确定为无缺陷的程序的信号处理的信号处理电路的第一半导体器件进行排序。 分类器件被组装为一体的半导体器件。 在用于测试的电路板上，提供与半导体器件的实际操作相当的时钟信号。 用于对第一存储器电路进行性能测试的测试程序从测试器写入第二半导体器件的第二存储器电路。 在信号处理电路中，根据与时钟信号对应的写入测试程序对第一存储器电路进行性能测试。 在该性能测试中，故障/无故障确定的结果被输出到测试器。

公开(公告)号：US20080303173A1

公开(公告)日：2008-12-11

申请号：US12127788

申请日：2008-05-27

申请人： Kanya HAMADA ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

发明人： Kanya HAMADA ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

IPC分类号： H01L21/66 ,  G01R31/26 ,  H01L23/52

CPC分类号： H01L22/20 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318583 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.

摘要翻译： 提供了用于小型化的SiP或PoP的半导体器件，其制造方法以及适用于实现系统的简化和提高效率的SiP和PoP的测试方法。 对包括被确定为无缺陷的第一存储器电路和包括第二存储器电路的第二半导体器件和执行被确定为无缺陷的程序的信号处理的信号处理电路的第一半导体器件进行排序。 分类器件被组装为一体的半导体器件。 在用于测试的电路板上，提供与半导体器件的实际操作相当的时钟信号。 用于对第一存储器电路进行性能测试的测试程序从测试器写入第二半导体器件的第二存储器电路。 在信号处理电路中，根据与时钟信号对应的写入测试程序对第一存储器电路进行性能测试。 在该性能测试中，故障/无故障确定的结果被输出到测试器。

公开(公告)号：US5692741A

公开(公告)日：1997-12-02

申请号：US549265

申请日：1995-10-27

申请人： Hidenobu Nakamura ,  Koji Naito ,  Yoshiaki Nakajima

发明人： Hidenobu Nakamura ,  Koji Naito ,  Yoshiaki Nakajima

IPC分类号： B65H5/06 ,  B65H7/20 ,  B65H5/00

CPC分类号： B65H7/20 ,  B65H5/062 ,  B65H2511/30 ,  B65H2513/10 ,  B65H2513/50 ,  B65H2557/61

摘要： In an operation for transporting a sheet by a first roller to a second roller pair downstream of the first roller, and further transporting the sheet by the second roller pair, the time during which the sheet is transported by the first roller is controlled, responsive to a comparison of a reference time and the actual time required for a sheet to be transported from the first roller to a predetermined position in the sheet transport path, to suppress disadvantages such as jamming and deformation into a Z-form, which may be caused by reduction of a transporting performance due to wear of the rollers and adhesion of paper powder to the rollers.

摘要翻译： 在通过第一辊将片材输送到第一辊子下游的第二辊对的操作中，并且通过第二辊对进一步输送片材时，控制片材由第一辊子传送的时间，响应于 参考时间与从第一辊到纸张传送路径中的预定位置传送的片材的实际时间的比较，以抑制诸如由Z形形成的阻塞和变形的缺点，这可能是由 减少由于辊的磨损和纸粉粘附到辊子上的运输性能。

公开(公告)号：US4852693A

公开(公告)日：1989-08-01

申请号：US229135

申请日：1988-08-05

申请人： Yoshiaki Nakajima ,  Tadashi Suzuki ,  Yoneji Wada

发明人： Yoshiaki Nakajima ,  Tadashi Suzuki ,  Yoneji Wada

IPC分类号： F16N29/04

CPC分类号： F16N29/04

摘要： A lubrication monitoring apparatus for a machine, in which an oil pressure gauge detects the pressure of lubricating oil of the filter, a first oil thermometer detects the temperature of lubricating oil before lubricating the mechanical section, a second oil thermometer detects the temperature of lubricating oil in the vicinity of the outlet of the lubricated mechanical section, and a warning device gives warning when any of the oil pressure, oil temperature, and oil temperature difference is out of a predetermined range.

公开(公告)号：US4605327A

公开(公告)日：1986-08-12

申请号：US758055

申请日：1985-07-23

申请人： Junzo Ueki ,  Yoshiaki Nakajima

发明人： Junzo Ueki ,  Yoshiaki Nakajima

IPC分类号： B41J32/00 ,  B41J33/52

CPC分类号： B41J32/00 ,  B41J33/52

摘要： A print ribbon cassette of a simplified construction which can prevent slackening of a print ribbon and normally keep the print ribbon in taut condition for printing. The print ribbon cassette comprises a lock member having a locking position for preventing inadvertent rotation of a feed spool on which a print ribbon to be supplied is wound. The cassette further comprises a ribbon lock control member which is moved between an operative position and an inoperative position in response to a tensile force of a print ribbon applied thereto. In the operative position of the ribbon lock control member, it engages with the lock member and holds the same to the lock position.

摘要翻译： 一种简化结构的打印色带盒，可以防止打印色带松弛，并且通常保持打印色带处于打印状态。 打印色带盒包括锁定构件，该锁定构件具有锁定位置，用于防止在其上卷绕要供应的打印色带的进给卷轴的意外旋转。 盒还包括色带锁定控制构件，其响应于施加到其上的打印色带的张力而在操作位置和不工作位置之间移动。 在色带锁定控制构件的操作位置，其与锁定构件接合并将其保持在锁定位置。

公开(公告)号：US20110018573A1

公开(公告)日：2011-01-27

申请号：US12895649

申请日：2010-09-30

申请人： Kanya HAMADA ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

发明人： Kanya HAMADA ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

IPC分类号： G01R31/26

CPC分类号： H01L22/20 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318583 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SIP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.

摘要翻译： 提供了一种用于小型化的SiP或PoP的半导体器件，其制造方法以及适用于实现系统简化和提高其效率的SIP和PoP的测试方法。 对包括被确定为无缺陷的第一存储器电路和包括第二存储器电路的第二半导体器件和执行被确定为无缺陷的程序的信号处理的信号处理电路的第一半导体器件进行排序。 分类器件被组装为一体的半导体器件。 在用于测试的电路板上，提供与半导体器件的实际操作相当的时钟信号。 用于对第一存储器电路进行性能测试的测试程序从测试器写入第二半导体器件的第二存储器电路。 在信号处理电路中，根据与时钟信号对应的写入测试程序对第一存储器电路进行性能测试。 在该性能测试中，故障/无故障确定的结果被输出到测试器。

公开(公告)号：US07816154B2

公开(公告)日：2010-10-19

申请号：US12127788

申请日：2008-05-27

申请人： Kanya Hamada ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

发明人： Kanya Hamada ,  Tasuke Tanaka ,  Akira Seito ,  Yoshiaki Nakajima

IPC分类号： H01L21/66 ,  H01L21/44

CPC分类号： H01L22/20 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318583 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SiP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device. In the signal processing circuit, a performance test is conducted on the first memory circuit according to the written test program in correspondence with the clock signal. The result of failure/no-failure determination in this performance test is outputted to the tester.

摘要翻译： 提供了用于小型化的SiP或PoP的半导体器件，其制造方法以及适用于实现系统的简化和提高效率的SiP和PoP的测试方法。 对包括被确定为无缺陷的第一存储器电路和包括第二存储器电路的第二半导体器件和执行被确定为无缺陷的程序的信号处理的信号处理电路的第一半导体器件进行排序。 分类器件被组装为一体的半导体器件。 在用于测试的电路板上，提供与半导体器件的实际操作相当的时钟信号。 用于对第一存储器电路进行性能测试的测试程序从测试器写入第二半导体器件的第二存储器电路。 在信号处理电路中，根据与时钟信号对应的写入测试程序对第一存储器电路进行性能测试。 在该性能测试中，故障/无故障确定的结果被输出到测试器。

公开(公告)号：US07487708B2

公开(公告)日：2009-02-10

申请号：US11138721

申请日：2005-05-26

申请人： Yasuo Harashima ,  Yoshiaki Nakajima ,  Hiroshi Gunji

发明人： Yasuo Harashima ,  Yoshiaki Nakajima ,  Hiroshi Gunji

IPC分类号： F15B15/24

CPC分类号： F15B15/24

摘要： The female screw (8a) is formed on the inner circumference of the forward side of the piston receiving hole (8) in the cylinder body (2) and the movable stopper (9) is screwed into the female screw (8a). The piston (12) is located at the stroke end of the forward side when its end face of the forward side is contact with the end face of the backward side of the movable stopper (9). The rotating knob (4) is rotatably mounted on the end of the forward side of the cylinder body (2). The rotation transmitting pin (16) is projected on the end face of the backward side of the rotating knob. The rotation transmitting hole (9a) is formed on the end face of the forward side of the movable stopper (9). The rotation transmitting pin (16) is slidably inserted into the rotation transmitting hole. When the rotating knob (4) is rotated, the movable stopper (9) is screwed into so that the stroke end position and the moving stroke of the piston (12) can be adjusted.

摘要翻译： 内螺纹（8a）形成在缸体（2）中的活塞接收孔（8）的前侧的内周上，可动止动件（9）旋入阴螺纹（8a）中。 当其前端的端面与可动止动件（9）的后侧的端面接触时，活塞（12）位于前侧的行程端。 旋转旋钮（4）可旋转地安装在气缸体（2）的前侧的端部。 旋转传递销（16）突出在旋钮的后侧的端面上。 旋转传递孔（9a）形成在可动止动件（9）的前侧的端面上。 旋转传递销（16）可滑动地插入旋转传递孔。 当旋转旋钮（4）旋转时，可动止动器（9）被拧入，从而可以调整活塞（12）的行程终点位置和移动行程。

公开(公告)号：US20140004225A1

公开(公告)日：2014-01-02

申请号：US14005857

申请日：2012-03-21

申请人： Hiroyuki Akamatsu ,  Yoshikazu Endo ,  Yoshiaki Nakajima ,  Toshifumi Matsuda ,  Shigeki Tanizawa

发明人： Hiroyuki Akamatsu ,  Yoshikazu Endo ,  Yoshiaki Nakajima ,  Toshifumi Matsuda ,  Shigeki Tanizawa

IPC分类号： A23L1/238

CPC分类号： A23L27/50

摘要： The present invention addresses the problem of obtaining a very low common salt soy sauce which contains flavor component favorable for a soy sauce at high concentrations and has a common salt concentration of 1.0 to 4.0% (w/v) and an ethanol concentration of 8.0 to 20% (v/v) without using any special means. According to the present invention, in a method for producing a soy sauce, a carbohydrate raw material and water or an aqueous common salt solution are added to a first moromi, in which the viable soy sauce yeast cell count per 1 g of moromi is 1×107 cells or more, followed by fermentation to prepare a second moromi having a common salt concentration of 4.0 to 12.0% (w/v) and an ethanol concentration of 4.0 to 12.0% (v/v), and then, a carbohydrate raw material and water or an aqueous common salt solution are added thereto to prepare a third moromi, in which the viable yeast cell count per 1 g of moromi is 2×106 cells or more, and which has an ethanol concentration of 2.0% (v/v) or more, by further adding yeast or without adding yeast, followed by fermentation and maturation, thereby obtaining the very low common salt soy sauce.

摘要翻译： 本发明解决了获得非常低的普通盐酱油的问题，其含有高浓度酱油的调味成分，其盐浓度为1.0〜4.0％（w / v），乙醇浓度为8.0〜 20％（v / v），不使用任何特殊手段。 根据本发明，在酱油的制造方法中，将碳水化合物原料和水或普通盐水溶液加入到每1g莫诺米的活的酱油酵母细胞计数为1的第一醪液中 ×10 7个细胞以上，然后发酵，制备盐浓度为4.0〜12.0％（w / v），乙醇浓度为4.0〜12.0％（v / v）的第二醪液， 向其中加入材料和水或含水盐溶液以制备其中每1g莫诺米的活酵母细胞计数为2×10 6个细胞或更多，并且其乙醇浓度为2.0％（v / v）以上，进一步添加酵母或不添加酵母，进行发酵成熟，得到非常低的普通盐酱油。