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29 条记录 (耗时 0.021 秒)

    Image data storage/processing apparatus
    2.
    发明授权
    Image data storage/processing apparatus 失效
    图像数据存储/处理装置

    公开(公告)号：US5428389A

    公开(公告)日：1995-06-27

    申请号：US104928

    申请日：1993-08-12

    申请人： Kenji Ito ,  Kaoru Adachi ,  Osamu Saito

    发明人： Kenji Ito ,  Kaoru Adachi ,  Osamu Saito

    IPC分类号： G11C7/10 ,  H04N1/21 ,  H04N7/30 ,  H04N5/76 ,  H04N9/64

    CPC分类号： H04N1/2137 ,  G11C7/1027 ,  H04N1/2112 ,  H04N1/2158 ,  H04N19/60

    摘要： An image data storage/processing apparatus is provided, which is particularly applicable to an electronic still camera, for example. The image data storage apparatus uses a dynamic RAM as a frame memory for temporarily storing image data representative of a field of an image to be recorded. The frame memory includes at least first and second memories. In the apparatus, there is provided a control so that the image data corresponding to the adjacent two pixel lines on the field are continuously read out in such a manner that they are simultaneously read out from the first and second memories, and the image data corresponding to one of the two pixel lines are read out with delay by the time required for reading out of the image data corresponding to the other pixel line. The image signal processing apparatus is capable of performing processing for writing in and reading out of various types of image data with a single memory.

    摘要翻译： 提供了一种特别适用于电子静态照相机的图像数据存储/处理装置。 图像数据存储装置使用动态RAM作为帧存储器，用于临时存储表示要记录的图像的场的图像数据。 帧存储器至少包括第一和第二存储器。 在该装置中，提供了一种控制，使得对应于场上的相邻两个像素线的图像数据以从第一和第二存储器同时读出的方式连续地读出，并且图像数据对应 到两个像素线中的一个被延迟地读出对应于另一个像素线的图像数据所需的时间。 图像信号处理装置能够执行用单个存储器写入和读出各种图像数据的处理。

    Surface hardened aluminum part and method of producing same
    3.
    发明授权
    Surface hardened aluminum part and method of producing same 失效
    表面硬化铝部件及其制造方法

    公开(公告)号：US5352538A

    公开(公告)日：1994-10-04

    申请号：US937266

    申请日：1992-08-31

    申请人： Toshihide Takeda ,  Kaoru Adachi

    发明人： Toshihide Takeda ,  Kaoru Adachi

    IPC分类号： C23C24/08 ,  B22F7/08 ,  C23C24/10 ,  C23C26/00 ,  C23C26/02 ,  F02F3/12 ,  B22F7/04

    CPC分类号： B22F7/08 ,  C23C24/103 ,  C23C26/02 ,  F02F3/12 ,  F05C2201/021 ,  F05C2201/0448 ,  Y10T428/12014 ,  Y10T428/12049 ,  Y10T428/12056 ,  Y10T428/12063 ,  Y10T428/12139

    摘要： A surface hardened aluminum part having excellent heat resistance and abrasion resistance obtained by forming, on the surface of an aluminum base material, an alloy layer that has a uniform composition and uniform hardness, being free from cracks. An aluminum alloy powder made of aluminum and metals each of which forms an intermetallic compound of high hardness with aluminum is prepared. This aluminum alloy powder is supplied onto the aluminum base material and the aluminum or aluminum alloy contained in the aluminum base material is alloyed with the aluminum alloy powder using a high-density energy heat source to form an alloy layer. The alloy layer thus formed has an intermetallic compound of high hardness uniformly distributed throughout the layer so that the hardness of the alloy layer is uniform and cracking is unlikely to occur.

    摘要翻译： 通过在铝基材的表面上形成具有均匀组成和均匀硬度的合金层，没有裂纹而获得的具有优异的耐热性和耐磨性的表面硬化铝部分。 制备由铝和金属制成的铝合金粉末，每种铝粉均与铝形成高硬度的金属间化合物。 将该铝合金粉末供给到铝基材上，使用高密度能量热源将包含在铝基材中的铝或铝合金与铝合金粉末合金化，形成合金层。 如此形成的合金层具有均匀分布在整个层中的高硬度的金属间化合物，使得合金层的硬度是均匀的，并且不可能发生开裂。

    Method of recording data in memory card having EEPROM and memory card system using the same
    4.
    发明授权
    Method of recording data in memory card having EEPROM and memory card system using the same 失效
    在具有EEPROM的存储卡和使用其的存储卡系统中记录数据的方法

    公开(公告)号：US5303198A

    公开(公告)日：1994-04-12

    申请号：US726173

    申请日：1991-07-05

    申请人： Kaoru Adachi ,  Kouichi Gouhara

    发明人： Kaoru Adachi ,  Kouichi Gouhara

    IPC分类号： G06K19/07 ,  G11C16/10 ,  G11C7/00

    CPC分类号： G11C16/105 ,  G06K19/07 ,  G11C16/102 ,  G06F2212/2022

    摘要： A method of recording data in a memory card having an EEPROM, and a memory card system using the same are provided. A memory card has at least two collective erasure type EEPROM chips where at least one of which is conditioned for a spare memory. When an access of the kind needing overwriting is made to the memory card, data stored in memory locations of the addresses of a corresponding EEPROM chip, except for the address where overwriting is to occur, are copied in the spare memory, and then the EEPROM chip of interest and the spare memory are replaced with each other. The EEPROM chips may be replaced with a plurality of memory blocks or clusters defined in a block erasure type EEPROM.

    摘要翻译： 提供了一种在具有EEPROM的存储卡中记录数据的方法和使用其的存储卡系统。 存储卡具有至少两个集体擦除型EEPROM芯片，其中至少一个被调节为备用存储器。 当对存储卡进行需要覆盖的存取时，存储在相应的EEPROM芯片的地址的存储位置中的数据除了要进行重写的地址之外，被复制到备用存储器中，然后EEPROM 感兴趣的芯片和备用存储器被彼此替换。 EEPROM芯片可以用在块擦除型EEPROM中定义的多个存储器块或簇代替。

    Integrated circuit and method of controlling same
    7.
    发明授权
    Integrated circuit and method of controlling same 失效
    集成电路及其控制方法

    公开(公告)号：US06959357B2

    公开(公告)日：2005-10-25

    申请号：US09852683

    申请日：2001-05-11

    申请人： Kaoru Adachi

    发明人： Kaoru Adachi

    IPC分类号： G06F3/00 ,  G06F13/36 ,  G06F13/40 ,  G06F13/00 ,  G06F1/06

    CPC分类号： G06F13/4022

    摘要： Bus-connected circuits are made to operate stably and at high speed. A cache memory for high-speed access and a DRAM for low-speed access are connected to a CPU by an address bus, control bus and data transfer bus. A switch is provided in the bus at a point between the cache memory and DRAM and the switch is opened at the time of high-speed access. Since bus length is essentially shortened at such time, the cache memory can be accessed stably at high speed. When the DRAM is accessed, the switch is closed.

    摘要翻译： 总线连接电路可以稳定和高速运行。 用于高速存取的高速缓冲存储器和用于低速​​存取的DRAM通过地址总线，控制总线和数据传输总线连接到CPU。 在高速缓冲存储器和DRAM之间的点处在总线中提供开关，并且在高速访问时打开开关。 由于总线长度在这样的时间基本上被缩短，所以高速缓冲存储器可以被高速稳定地访问。 当DRAM被访问时，开关闭合。

    Laser welding method
    8.
    发明授权
    Laser welding method 失效
    激光焊接方法

    公开(公告)号：US06744007B2

    公开(公告)日：2004-06-01

    申请号：US10050832

    申请日：2002-01-18

    申请人： Kazuhiko Ono ,  Kaoru Adachi ,  Tairou Samejima ,  Akitoshi Masamura

    发明人： Kazuhiko Ono ,  Kaoru Adachi ,  Tairou Samejima ,  Akitoshi Masamura

    IPC分类号： B23K2026

    CPC分类号： B23K26/24 ,  B23K26/211

    摘要： This invention provides a laser welding method capable of supplying a filler wire to a welding object portion in a stabilized condition so as to stabilize welding quality. More specifically, the filler wire is supplied to the welding object portion while the laser beam is projected to the welding object portion. At this time, the filler wire is supplied obliquely from forward or backward in the welding advance direction such that the angle between the supplying direction and beam axis L of the laser beam is less than 45°.

    摘要翻译： 本发明提供一种激光焊接方法，其能够在稳定状态下向焊接对象部供给填充焊丝，以稳定焊接质量。 更具体地，当激光束投射到焊接对象部分时，将填充焊丝提供给焊接对象部分。 此时，在焊接前进方向上，从前后方向倾斜地供给填充线，使得激光束的供给方向与光束轴L之间的角度小于45°。

    IC memory card system having a common data and address bus
    10.
    发明授权
    IC memory card system having a common data and address bus 失效
    具有公共数据和地址总线的IC存储卡系统

    公开(公告)号：US5361228A

    公开(公告)日：1994-11-01

    申请号：US54575

    申请日：1993-04-30

    申请人： Kaoru Adachi ,  Katsuya Makioka

    发明人： Kaoru Adachi ,  Katsuya Makioka

    IPC分类号： G06K19/073 ,  G11C5/06 ,  G11C16/10 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C16/102 ,  G11C5/066

    摘要： An IC memory card system has a host for processing data, and an IC memory card removably connected to the host and incorporating a data recording medium implemented by an electrically erasable programmable semiconductor memory. The host comprises a system controller for sending to the memory card an address/data signal for distinguishing an address and data by a logical bilevel state, a read/write signal for distinguishing reading of data and writing of data in the semiconductor memory by a logical bilevel state, and an erase signal for erasing data stored in the semiconductor memory by a logical bilevel state as control signals, and bus clock pulses each being synchronous to a particular address and particular data. The IC memory card comprises a control circuit responsive to the address/data signal, read/write signal, erase signal and bus clock pulses for distinguishing an address and data, distinguishing reading and writing, and determining whether or not to erase existing data, and then reading or writing data in the semiconductor memory or erasing the existing data.

    摘要翻译： IC存储卡系统具有用于处理数据的主机，以及可移除地连接到主机并且并入由电可擦除可编程半导体存储器实现的数据记录介质的IC存储卡。 主机包括系统控制器，用于向存储卡发送用于区分地址和数据的逻辑双电平状态的地址/数据信号，用于区分数据读取和半导体存储器中的数据写入的逻辑的读/写信号 二级状态，以及擦除信号，用于通过逻辑二级状态擦除存储在半导体存储器中的数据作为控制信号，以及每个与特定地址和特定数据同步的总线时钟脉冲。 IC存储卡包括响应于地址/数据信号，读/写信号，擦除信号和总线时钟脉冲的控制电路，用于区分地址和数据，区分读和写，以及确定是否擦除现有数据，以及 然后读取或写入半导体存储器中的数据或擦除现有数据。