公开(公告)号：US20060289852A1

公开(公告)日：2006-12-28

申请号：US11511047

申请日：2006-08-28

申请人： Gregory Freeman ,  Marwan Khater ,  Rajendran Krishnasamy ,  Kathryn Schonenberg ,  Andreas Stricker

发明人： Gregory Freeman ,  Marwan Khater ,  Rajendran Krishnasamy ,  Kathryn Schonenberg ,  Andreas Stricker

IPC分类号： H01L31/00

CPC分类号： H01L29/66068 ,  H01L29/2003 ,  H01L29/66242

摘要： A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.

摘要翻译： 提供了通过不包括C离子注入的方法将C并入到异质结双极器件的集电极区域中的结构和方法。 在本发明中，通过在刻蚀到集电极区域的周边沟槽中外延生长将C引入集电体，以更好地控制碳分布和位置。 通过使用沟槽隔离区域将集电极区域和在集电体的中心部分上的图案化层作为掩模来形成沟槽。 然后，使用沟槽内部的选择性外延生长Si：C以形成具有清晰且明确界定的边缘的Si：C区域。 可以优化深度，宽度和C含量以控制和定制集电极注入扩散并减少寄生C CB的周边分量。

公开(公告)号：US20050079726A1

公开(公告)日：2005-04-14

申请号：US10969718

申请日：2004-10-20

申请人： Huajie Chen ,  Kathryn Schonenberg ,  Gregory Freeman ,  Andreas Stricker ,  Jae-Sung Rieh

发明人： Huajie Chen ,  Kathryn Schonenberg ,  Gregory Freeman ,  Andreas Stricker ,  Jae-Sung Rieh

IPC分类号： H01L21/321 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L21/32105 ,  Y10S438/911

摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.

公开(公告)号：US20050054171A1

公开(公告)日：2005-03-10

申请号：US10953378

申请日：2004-09-29

申请人： Jack Chu ,  Douglas Coolbaugh ,  James Dunn ,  David Greenberg ,  David Harame ,  Basanth Jagannathan ,  Robb Johnson ,  Louis Lanzerotti ,  Kathryn Schonenberg ,  Ryan Wuthrich

发明人： Jack Chu ,  Douglas Coolbaugh ,  James Dunn ,  David Greenberg ,  David Harame ,  Basanth Jagannathan ,  Robb Johnson ,  Louis Lanzerotti ,  Kathryn Schonenberg ,  Ryan Wuthrich

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

摘要翻译： 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

公开(公告)号：US20060154476A1

公开(公告)日：2006-07-13

申请号：US10905510

申请日：2005-01-07

申请人： Gregory Freeman ,  Marwan Khater ,  Rajendran Krishnasamy ,  Kathryn Schonenberg ,  Andreas Stricker

发明人： Gregory Freeman ,  Marwan Khater ,  Rajendran Krishnasamy ,  Kathryn Schonenberg ,  Andreas Stricker

IPC分类号： H01L21/4763

CPC分类号： H01L29/66068 ,  H01L29/2003 ,  H01L29/66242

摘要： A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.

摘要翻译： 提供了通过不包括C离子注入的方法将C并入到异质结双极器件的集电极区域中的结构和方法。 在本发明中，通过在刻蚀到集电极区域的周边沟槽中外延生长将C引入集电体，以更好地控制碳分布和位置。 通过使用沟槽隔离区域将集电极区域和在集电体的中心部分上的图案化层作为掩模来形成沟槽。 然后，使用沟槽内部的选择性外延生长Si：C以形成具有清晰且明确界定的边缘的Si：C区域。 可以优化深度，宽度和C含量以控制和定制集电极注入扩散并减少寄生C CB的周边分量。

公开(公告)号：US20060252216A1

公开(公告)日：2006-11-09

申请号：US10908363

申请日：2005-05-09

申请人： Omer Dokumaci ,  Gregory Freeman ,  Marwan Khater ,  Rajendran Krishnasamy ,  Kathryn Schonenberg

发明人： Omer Dokumaci ,  Gregory Freeman ,  Marwan Khater ,  Rajendran Krishnasamy ,  Kathryn Schonenberg

IPC分类号： H01L21/331

CPC分类号： H01L29/7378 ,  H01L29/0821 ,  H01L29/66242

摘要： Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.

摘要翻译： 提供双极晶体管，特别是SiGe异质结双极晶体管的性能的方法与通过本发明方法形成的结构一起提供。 所述方法包括向至少一个收集器提供包含C，惰性气体或其混合物的富含物质的掺杂剂区域。 富含物质的掺杂剂区域围绕收集器的中心部分形成周边或环形掺杂剂区域。 然后将第一导电型掺杂剂注入到集电极的中心部分中，以形成由外部富物质掺杂区域横向约束，即限制的第一导电型掺杂剂区域。

公开(公告)号：US20060231924A1

公开(公告)日：2006-10-19

申请号：US11169444

申请日：2005-06-29

申请人： Thomas Adam ,  Kevin Chan ,  Alvin Joseph ,  Marwan Khater ,  Qizhi Liu ,  Beth Rainey ,  Kathryn Schonenberg

发明人： Thomas Adam ,  Kevin Chan ,  Alvin Joseph ,  Marwan Khater ,  Qizhi Liu ,  Beth Rainey ,  Kathryn Schonenberg

IPC分类号： H01L21/331 ,  H01L27/082 ,  H01L27/102 ,  H01L31/11

CPC分类号： H01L29/7378 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287

摘要： The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

摘要翻译： 本发明包括制造双极晶体管的方法，该双极晶体管在形成连接层之前，将硅锗（SiGe）层或例如高压氧化物（HIPOX）的第三绝缘体层与邻近本征基极的发射极帽顶上相加 。 该添加允许使用湿蚀刻化学去除连接层，以去除在不使用氧化的情况下形成在发射极帽顶上的多余SiGe或第三绝缘体层。 在这种情况下，可以使用氧化物部分（通过沉积氧化物或上述HIPOX层的分离）和氮化物间隔物形成发射极 - 基极隔离。 本发明导致较低的热循环，较低的应力水平和对发射极盖层厚度的更多控制，这是第一实施例的缺点。 本发明还包括所得到的双极晶体管结构。

公开(公告)号：US20050151225A1

公开(公告)日：2005-07-14

申请号：US10904482

申请日：2004-11-12

申请人： Thomas Adam ,  Kevin Chan ,  Alvin Joseph ,  Marwan Khater ,  Qizhi Liu ,  Beth Rainey ,  Kathryn Schonenberg

发明人： Thomas Adam ,  Kevin Chan ,  Alvin Joseph ,  Marwan Khater ,  Qizhi Liu ,  Beth Rainey ,  Kathryn Schonenberg

IPC分类号： H01L21/331 ,  H01L29/10

CPC分类号： H01L29/7378 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287

摘要： The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

摘要翻译： 本发明包括制造双极晶体管的方法，该双极晶体管在形成连接层之前，将硅锗（SiGe）层或例如高压氧化物（HIPOX）的第三绝缘体层与邻近本征基极的发射极帽顶上相加 。 该添加允许使用湿蚀刻化学去除连接层，以去除在不使用氧化的情况下形成在发射极帽顶上的多余SiGe或第三绝缘体层。 在这种情况下，可以使用氧化物部分（通过沉积氧化物或上述HIPOX层的分离）和氮化物间隔物形成发射极 - 基极隔离。 本发明导致较低的热循环，较低的应力水平和对发射极盖层厚度的更多控制，这是第一实施例的缺点。 本发明还包括所得到的双极晶体管结构。

公开(公告)号：US20050151165A1

公开(公告)日：2005-07-14

申请号：US10707712

申请日：2004-01-06

申请人： Kevin Chan ,  Marwan Khater ,  Kathryn Schonenberg ,  Panda Siddhartha

发明人： Kevin Chan ,  Marwan Khater ,  Kathryn Schonenberg ,  Panda Siddhartha

IPC分类号： H01L21/331 ,  H01L29/10 ,  H01L29/737 ,  H01L29/739

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

摘要： A heterojunction bipolar transistor (HBT) and method of making an HBT are provided. The HBT includes a collector, and an intrinsic base overlying the collector. The intrinsic base includes a layer of a single-crystal semiconductor alloy. The HBT further includes a raised extrinsic base having a first semiconductive layer overlying the intrinsic base and a second semiconductive layer formed on the first semiconductive layer. An emitter overlies the intrinsic base, and is disposed in an opening of the first and second semi-conductive layers, such that the raised extrinsic base is self-aligned to the emitter.

摘要翻译： 提供异质结双极晶体管（HBT）和制造HBT的方法。 HBT包括收集器和覆盖收集器的本征基极。 本征基底包括一层单晶半导体合金。 HBT还包括凸起的非本征基底，其具有覆盖本征基底的第一半导体层和形成在第一半导体层上的第二半导体层。 发射极覆盖本征基极，并且设置在第一和第二半导体层的开口中，使得凸出的外基极与发射极自对准。