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    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT
    1.
    发明申请
    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT 失效
    集成薄膜电阻与直接接触

    公开(公告)号：US20070166909A1

    公开(公告)日：2007-07-19

    申请号：US11275611

    申请日：2006-01-19

    申请人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    发明人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    IPC分类号： H01L21/8244

    CPC分类号： H01L27/016

    摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. *Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

    摘要翻译： 适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。 第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。 同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

    INTEGRATION SCHEME FOR HIGH GAIN FET IN STANDARD CMOS PROCESS
    2.
    发明申请
    INTEGRATION SCHEME FOR HIGH GAIN FET IN STANDARD CMOS PROCESS 审中-公开
    标准CMOS工艺中高增益FET的集成方案

    公开(公告)号：US20070099386A1

    公开(公告)日：2007-05-03

    申请号：US11163791

    申请日：2005-10-31

    申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  James Slinkman ,  Michael Zierak

    发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  James Slinkman ,  Michael Zierak

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L29/66659 ,  H01L21/26586

    摘要： A method for fabricating high gain FETs that substantially reduces or eliminates unwanted variation in device characteristics caused by using a prior art shadow masking process is provided. The inventive method employs a blocking mask that at least partially extends over the gate region wherein after extension and halo implants an FET having an asymmetric halo region asymmetric extension regions or a combination thereof is fabricated. The inventive method thus provides high gain FETs in which the variation of device characteristics is substantially reduced. The present invention also relates to the resulting asymmetric high gain FET device that is fabricated utilizing the method of the present invention.

    摘要翻译： 提供了一种制造高增益FET的方法，其基本上减少或消除了由使用现有技术的阴影掩蔽处理引起的器件特性的不必要的变化。 本发明的方法采用阻挡掩模，其在栅极区域上至少部分地延伸，其中在延伸和卤素注入之后，制造具有不对称卤素区域不对称延伸区域或其组合的FET。 因此，本发明的方法提供了高增益FET，其中器件特性的变化显着降低。 本发明还涉及利用本发明的方法制造的非对称高增益FET器件。

    SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE
    3.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 有权
    半导体结构及其制造方法

    公开(公告)号：US20070096257A1

    公开(公告)日：2007-05-03

    申请号：US11163882

    申请日：2005-11-02

    申请人： Douglas Coolbaugh ,  Alvin Joseph ,  Seong-dong Kim ,  Louis Lanzerotti ,  Xuefeng Liu ,  Robert Rassel

    发明人： Douglas Coolbaugh ,  Alvin Joseph ,  Seong-dong Kim ,  Louis Lanzerotti ,  Xuefeng Liu ,  Robert Rassel

    IPC分类号： H01L27/102

    CPC分类号： H01L27/0814 ,  H01L27/0664 ,  H01L27/0823 ,  H01L29/0821 ,  H01L29/7371 ,  H01L29/868

    摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.

    摘要翻译： 一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。 还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。 该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。 第二掺杂区形成在与第一掺杂区不同的深度。 该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

    STRUCTURE AND METHOD FOR INTEGRATING MIM CAPACITOR IN BEOL WIRING LEVELS
    4.
    发明申请
    STRUCTURE AND METHOD FOR INTEGRATING MIM CAPACITOR IN BEOL WIRING LEVELS 失效
    将电容器集成在水平线上的结构和方法

    公开(公告)号：US20060189069A1

    公开(公告)日：2006-08-24

    申请号：US10906521

    申请日：2005-02-23

    申请人： Douglas Coolbaugh ,  Vidhya Ramachandran

    发明人： Douglas Coolbaugh ,  Vidhya Ramachandran

    IPC分类号： H01L21/8242 ,  H01L29/94

    CPC分类号： H01L23/5223 ,  H01L21/76808 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for integrating a metal-insulator-metal (MIM) capacitor in back end of line (BEOL) wiring levels of a semiconductor device includes forming an isolating layer over a lower wiring level, forming a bottom electrode of the capacitor on the isolating layer, and forming an interlevel dielectric material on the isolating layer and the bottom electrode. A capacitor dielectric is formed on the bottom electrode and a top electrode of the capacitor is formed on the capacitor dielectric, wherein the top electrode is formed concurrently with an upper wiring level, the upper level being the next successive wiring level with respect to the lower wiring level.

    摘要翻译： 在半导体器件的后端（BEOL）布线层中集成金属 - 绝缘体 - 金属（MIM）电容器的方法包括在下布线层上形成隔离层，在隔离层上形成电容器的底电极 并且在隔离层和底部电极上形成层间电介质材料。 在底部电极上形成电容器电介质，并且在电容器电介质上形成电容器的顶部电极，其中顶部电极与上部布线电平同时形成，上部电平是相对于下部电极的下一个连续布线电平 接线等级。

    MOS VARACTOR USING ISOLATION WELL
    7.
    发明申请
    MOS VARACTOR USING ISOLATION WELL 有权
    使用隔离的MOS变压器

    公开(公告)号：US20060043454A1

    公开(公告)日：2006-03-02

    申请号：US10711144

    申请日：2004-08-27

    申请人： Douglas Coolbaugh ,  Douglas Hershberger ,  Robert Rassel

    发明人： Douglas Coolbaugh ,  Douglas Hershberger ,  Robert Rassel

    IPC分类号： H01L29/94 ,  H01L21/20

    CPC分类号： H01L29/93 ,  H01L29/94

    摘要： The present invention provides a varactor that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate of a first conductivity type and optionally a subcollector or isolation well (i.e., doped region) of a second conductivity type located below an upper region of the substrate, the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions are formed in the upper region of the substrate and then a well region is formed in the upper region of the substrate. In some cases, the doped region is formed at this point of the inventive process. The well region includes outer well regions of the second conductivity type and an inner well region of the first conductivity type. Each well of said well region is separated at an upper surface by an isolation region. A field effect transistor having at least a gate conductor of the first conductivity type is then formed above the inner well region.

    摘要翻译： 本发明提供一种具有增加的可调性和高品质因数Q的变容二极管以及制造变容二极管的方法。 本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。 该方法包括提供包括第一导电类型的半导体衬底和位于衬底的上部区域下方的第二导电类型的子集电极或隔离阱（即，掺杂区）的结构，第一导电类型不同于 所述第二导电类型。 接下来，在基板的上部区域形成多个隔离区域，然后在基板的上部区域形成阱区域。 在一些情况下，在本发明方法的这一点形成掺杂区域。 阱区包括第二导电类型的外阱区和第一导电类型的内阱区。 所述阱区的每个阱在上表面被隔离区分开。 然后形成至少具有第一导电类型的栅极导体的场效应晶体管，并在内部阱区域的上方形成。

    RESISTOR TUNING
    9.
    发明申请
    RESISTOR TUNING 有权
    电阻调谐

    公开(公告)号：US20050230785A1

    公开(公告)日：2005-10-20

    申请号：US10709115

    申请日：2004-04-14

    申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  Anthony Stamper

    发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  Anthony Stamper

    IPC分类号： H01C17/26 ,  H01L29/76

    CPC分类号： H01C17/267

    摘要： A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact regions. A voltage difference is applied between the first and second contact regions. As a result, a current flows between the first and second contact regions in the electrically conducting region. The voltage difference and the materials of the electrically conducting region and the liner region are such that electromigration occurs only in the electrically conducting region. As a result, a void region within the electrically conducting region expands in the direction of the flow of the charged particles constituting the current. Because the resistor loses a conducting portion of the electrically conducting region to the void region, the resistance of the resistor is increased (i.e., tuned).

    摘要翻译： 电阻器结构及其调谐方法。 电阻器包括耦合到衬垫区域的导电区域。 导电区域和衬里区域都电耦合到第一和第二接触区域。 在第一和第二接触区域之间施加电压差。 结果，电流在导电区域中的第一和第二接触区域之间流动。 导电区域和衬垫区域的电压差和材料使得电迁移仅在导电区域中发生。 结果，导电区域内的空隙区域在构成电流的带电粒子的流动方向上膨胀。 因为电阻器将导电区域的导电部分损失到空隙区域，电阻器的电阻增加（即调谐）。