公开(公告)号：US06498376B1

公开(公告)日：2002-12-24

申请号：US08459831

申请日：1995-06-02

申请人： Masanori Miyagi ,  Haruo Konishi ,  Kazuaki Kubo ,  Yoshikazu Kojima ,  Toru Shimizu ,  Yutaka Saitoh ,  Toru Machida ,  Tetsuya Kaneko

发明人： Masanori Miyagi ,  Haruo Konishi ,  Kazuaki Kubo ,  Yoshikazu Kojima ,  Toru Shimizu ,  Yutaka Saitoh ,  Toru Machida ,  Tetsuya Kaneko

IPC分类号： H01L2976

CPC分类号： H01L29/78696 ,  H01L21/3226 ,  H01L21/823462 ,  H01L27/0705 ,  H01L29/1041 ,  H01L29/1045 ,  H01L29/66757

摘要： A MISFET is provided with a segmented channel comprising regions in which the channel is inverted by a first gate voltage and regions in which the channel is inverted by a second gate voltage. The MISFET is formed in a semiconductor substrate having a first conductivity type and the first inversion region of the channel has a first impurity concentration determined by the surface concentration of the substrate. The second inversion region of the channel has a second impurity concentration determined by doping an impurity to the region selected by a photolithographic process. The first and second inversion regions may be divided into a plurality of plane shapes and the threshold voltage of the MISFET is set to a desired value in accordance with the plane area ratio of the first and second inversion regions.

摘要翻译： MISFET设置有分段通道，该分段通道包括其中通道被第一栅极电压反相的区域和通道以第二栅极电压反相的区域。 MISFET形成在具有第一导电类型的半导体衬底中，沟道的第一反相区域具有由衬底的表面浓度确定的第一杂质浓度。 通道的第二反转区域具有通过将杂质掺杂到通过光刻工艺选择的区域而确定的第二杂质浓度。 第一反转区域和第二反转区域可以被划分成多个平面形状，并且根据第一和第二反转区域的平面面积比将MISFET的阈值电压设置为期望值。

公开(公告)号：US06306709B1

公开(公告)日：2001-10-23

申请号：US09270648

申请日：1999-03-16

申请人： Masanori Miyagi ,  Haruo Konishi ,  Kazuaki Kubo ,  Yoshikazu Kojima ,  Toru Shimizu ,  Yutaka Saitoh ,  Toru Machida ,  Tetsuya Kaneko

发明人： Masanori Miyagi ,  Haruo Konishi ,  Kazuaki Kubo ,  Yoshikazu Kojima ,  Toru Shimizu ,  Yutaka Saitoh ,  Toru Machida ,  Tetsuya Kaneko

IPC分类号： H01L21336

CPC分类号： H01L29/78696 ,  H01L21/3226 ,  H01L21/823462 ,  H01L27/0705 ,  H01L29/1041 ,  H01L29/1045 ,  H01L29/66757

摘要： In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. The channel region 104 having a first impurity concentration determined by a surface concentration of a P-type semiconductor substrate and a channel region 105 having a second impurity concentration determined by doping an impurity to the region selected by a pattern 106 of a mask for doping impurity by ion implantation and others are provided in a channel region of an N-type MOSFET on the P-type semiconductor substrate. The channel region 104 having the first impurity concentration and the channel region 105 having the second impurity concentration are divided into a plurality of plane shapes. The channel region of the same MOSFET may be structured by the plurality of plane shapes having the plurality of impurity concentrations as described above and a threshold voltage of the MOSFET may be readily set to a desired value in response to a plane area ratio of the area having the first impurity concentration and the area having the second impurity concentration, allowing to realize a high performance semiconductor integrated circuit device at low cost.

摘要翻译： 在MISFET中，在MISFET的沟道区域中设置沟道区域的沟道表面被第一栅极电压反转的区域和沟道表面由第二栅极电压反转的区域，作为其组成。 具有由P型半导体衬底的表面浓度确定的第一杂质浓度的通道区域104和通过掺杂杂质确定的第二杂质浓度的沟道区域105，所述沟道区域105由用于掺杂杂质的掩模的图案106选择的区域 通过离子注入等设置在P型半导体衬底上的N型MOSFET的沟道区中。 具有第一杂质浓度的沟道区域104和具有第二杂质浓度的沟道区域105被分成多个平面形状。 相同MOSFET的沟道区域可以由具有如上所述的多个杂质浓度的多个平面形状构成，并且可以根据区域的平面面积比容易地将MOSFET的阈值电压设置为期望值 具有第一杂质浓度和具有第二杂质浓度的面积，从而以低成本实现高性能半导体集成电路器件。

公开(公告)号：US5905291A

公开(公告)日：1999-05-18

申请号：US503828

申请日：1995-07-18

申请人： Fumiyasu Utsunomiya ,  Yutaka Saitoh ,  Naoto Saitoh ,  Jun Osanai ,  Haruo Konishi ,  Masanori Miyagi

发明人： Fumiyasu Utsunomiya ,  Yutaka Saitoh ,  Naoto Saitoh ,  Jun Osanai ,  Haruo Konishi ,  Masanori Miyagi

IPC分类号： H01L21/8247 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  H01L29/772

CPC分类号： H01L27/0214 ,  H01L27/0629

摘要： A semiconductor integrated circuit device comprises at least two MISFETs formed on a semiconductor substrate and connected in series in a diode connection. Each of the MISFETs has a source, a drain, a channel extending between the source and the drain, and a gate disposed over the channel through a gate insulating film. One of the MISFETs has a first threshold voltage, and the other of the MISFETs has a second threshold voltage lower than the first threshold voltage. A portion of the channel of the semiconductor substrate of each of the MISFETs has an impurity concentration equal to or less than 6.times.10.sup.14 atoms/cc.

摘要翻译： 半导体集成电路器件包括形成在半导体衬底上并以二极管连接串联连接的至少两个MISFET。 每个MISFET具有源极，漏极，在源极和漏极之间延伸的沟道，以及通过栅极绝缘膜设置在沟道上方的栅极。 一个MISFET具有第一阈值电压，另一个MISFET具有低于第一阈值电压的第二阈值电压。 每个MISFET的半导体衬底的沟道的一部分具有等于或小于6×10 14原子/ cc的杂质浓度。

公开(公告)号：US5663589A

公开(公告)日：1997-09-02

申请号：US314140

申请日：1994-09-28

申请人： Yutaka Saitoh ,  Jun Osanai ,  Yoshikazu Kojima ,  Kazutoshi Ishii

发明人： Yutaka Saitoh ,  Jun Osanai ,  Yoshikazu Kojima ,  Kazutoshi Ishii

IPC分类号： H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L29/76 ,  H01L21/04

CPC分类号： H01L27/0814 ,  Y10S257/907 ,  Y10S257/91

摘要： A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source region formed in a semiconductor substrate, the source regions and the substrate regions being electrically coupled to each other, the drain regions of at least two of the MOS transistors being electrically coupled, and the source regions of each of the MOS transistors being electrically coupled, the coupled drain regions, the coupled source regions, and the coupled gates forming a drain terminal, a source terminal and a gate terminal, respectively. In order to set a desired regulated current, selected coupling lines in the current regulating diode may be cut. This may be accomplished, for example, by measuring a first current which flows in the drain terminal while applying a first voltage to the gate terminal and a second voltage to the drain terminal relative to an electric potential of the source terminal, then measuring a second current which flows in the drain terminal while applying a third voltage to the gate terminal and the second voltage to the drain terminal relative to an electric potential of the source terminal. In order to achieve the desired current characteristic, selected conductive lines between coupled drains or between coupled sources are then cut.

摘要翻译： 具有电流调节二极管的半导体集成器件可以通过形成多个MOS晶体管的电流调节二极管来大大减小尺寸并提高其性能，每个MOS晶体管具有形成在半导体衬底中的栅极，漏极区域和源极区域， 源极区域和衬底区域彼此电耦合，至少两个MOS晶体管的漏极区域电耦合，并且每个MOS晶体管的源极区域电耦合，耦合的漏极区域，耦合的 源极区域和耦合栅极分别形成漏极端子，源极端子和栅极端子。 为了设定期望的调节电流，可以切断电流调节二极管中的选择的耦合线。 这可以例如通过测量在漏极端子中流动的第一电流，同时向栅极端子施加第一电压，并且相对于源极端子的电位向漏极端子施加第二电压，然后测量第二电压 相对于源极端子的电位向漏极端子施加第三电压而向漏极端子施加第三电压而流过漏极端子的电流。 为了实现期望的电流特性，然后切割耦合的漏极之间或耦合的源之间的选定的导线。

公开(公告)号：US6013940A

公开(公告)日：2000-01-11

申请号：US516627

申请日：1995-08-18

申请人： Hirofumi Harada ,  Jun Osanai ,  Yoshikazu Kojima ,  Yutaka Saitoh

发明人： Hirofumi Harada ,  Jun Osanai ,  Yoshikazu Kojima ,  Yutaka Saitoh

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L27/06 ,  H01L27/08 ,  H01L29/00

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802

摘要： A resistor ladder network may be formed with a reduced space on a semiconductor substrate by patterning a plurality of layers of resistive polycrystalline silicon films spaced by insulating layers. Such a device includes a first insulating film formed on a semiconductor substrate, one or more serial-connected first resistors formed in a first polycrystalline silicon film provided on the semiconductor substrate via the first insulating film, a second insulating film provided on the first polycrystalline silicon film, one or more series-connected second resistors formed in a second polycrystalline silicon film provided apart from the first polycrystalline silicon film via the second insulating film, the second polycrystalline silicon film being connected to the first polycrystalline silicon film. A third insulating film is provided over the second polycrystalline silicon film, and metal wires provided on a surface of the second polycrystalline silicon film via contact holes formed in the third insulating film. Preferably, the first polycrystalline silicon film is thicker than the second polycrystalline silicon film, the impurity concentration of the first polycrystalline silicon film is lower than the impurity concentration of the second polycrystalline silicon film, and the grain size of the first polycrystalline silicon film is smaller than that of the second polycrystalline silicon film.

摘要翻译： 可以通过对由绝缘层隔开的多层电阻多晶硅膜进行构图而在半导体衬底上形成具有减小的空间的电阻梯形网络。 这种器件包括形成在半导体衬底上的第一绝缘膜，经由第一绝缘膜形成在设置在半导体衬底上的第一多晶硅膜中的一个或多个串联连接的第一电阻器，设置在第一多晶硅上的第二绝缘膜 膜，一个或多个串联连接的第二电阻器，形成在通过第二绝缘膜与第一多晶硅膜分开设置的第二多晶硅膜中，第二多晶硅膜连接到第一多晶硅膜。 在第二多晶硅膜上设置第三绝缘膜，通过形成在第三绝缘膜中的接触孔，设置在第二多晶硅膜的表面上的金属线。 优选地，第一多晶硅膜比第二多晶硅膜厚，第一多晶硅膜的杂质浓度低于第二多晶硅膜的杂质浓度，第一多晶硅膜的晶粒尺寸较小 比第二多晶硅膜的厚度大。

公开(公告)号：US07787915B2

公开(公告)日：2010-08-31

申请号：US11571747

申请日：2005-07-12

申请人： Hiroyuki Uejima ,  Yutaka Isoda ,  Nobuharu Mashima ,  Masayoshi Hirai ,  Nobuhiro Iwai ,  Yutaka Saitoh ,  Kenichi Maeda

发明人： Hiroyuki Uejima ,  Yutaka Isoda ,  Nobuharu Mashima ,  Masayoshi Hirai ,  Nobuhiro Iwai ,  Yutaka Saitoh ,  Kenichi Maeda

IPC分类号： H04M1/00

CPC分类号： H01Q1/243 ,  H01Q9/285 ,  H01Q9/42 ,  H04M1/0216

摘要： In a folding mobile radio device, a gain is lowered considerably in its close state under such a condition that an upper case is excited directly in its open state to aim at a wide band and a high gain is used as an antenna. A folding mobile radio device includes a first case, a second case, a jointing portion for connecting the first case and the second case to open/close, a conductor element arranged in the first case, and a feeding element arranged in the second case. Then, in an open state via the jointing portion, the conductor element and the feeding element come close to each other and are coupled magnetically at a time of feeding a power whereas, in a close state via the jointing portion, the conductor element and the feeding element are apart from each other rather than the open state and are not coupled magnetically at a time of feeding a power.

摘要翻译： 在折叠式移动无线电设备中，在大气体在其打开状态下被直接激发以对准宽带并且高增益被用作天线的条件下，在其接近状态下，增益显着降低。 折叠移动无线电设备包括第一壳体，第二壳体，用于连接第一壳体和第二壳体以打开/关闭的接合部分，布置在第一壳体中的导体元件和布置在第二壳体中的馈送元件。 然后，通过接合部处于断开状态，导体元件和馈电元件彼此接近并且在馈电时磁耦合，而在接合状态下，通过接合部分导体元件和 馈电元件彼此分开而不是打开状态，并且在馈送电力时不会磁耦合。

公开(公告)号：US20070109581A1

公开(公告)日：2007-05-17

申请号：US11593590

申请日：2006-11-07

申请人： Yutaka Saitoh

发明人： Yutaka Saitoh

IPC分类号： G06F3/12

CPC分类号： G06F3/1285 ,  G06F3/1208 ,  G06F3/1245 ,  G06F3/1256 ,  G06F3/1284

摘要： An information processing device converts input document data into print data used to control a printer, and displays a print preview before outputting the print data to the printer. In the information processing device, a document data storing unit stores the input document data as intermediate data. A layout determining unit determines a layout of image data of the document data on an output sheet based on a specified printing method, so that layout information is created. A preview displaying unit displays a print preview on a computer screen based on the stored document data. A print data creating unit converts the input document data into the print data.

摘要翻译： 信息处理设备将输入的文档数据转换为用于控制打印机的打印数据，并在将打印数据输出到打印机之前显示打印预览。 在信息处理设备中，文档数据存储单元将输入的文档数据存储为中间数据。 布局确定单元基于指定的打印方法在输出页上确定文档数据的图像数据的布局，从而创建布局信息。 预览显示单元基于存储的文档数据在计算机屏幕上显示打印预览。 打印数据创建单元将输入的文档数据转换成打印数据。

公开(公告)号：US20060052987A1

公开(公告)日：2006-03-09

申请号：US11206157

申请日：2005-08-18

申请人： Shozo Katsuki ,  Yutaka Saitoh ,  Tsutomu Tanaka ,  Akira Ohnishi ,  Sumitaka Tachikawa

发明人： Shozo Katsuki ,  Yutaka Saitoh ,  Tsutomu Tanaka ,  Akira Ohnishi ,  Sumitaka Tachikawa

IPC分类号： G06F15/00 ,  H03F1/26 ,  H04B15/00

CPC分类号： H04Q9/00

摘要： A wireless measuring device 1 is provided which includes a plurality of child units 2 and a parent unit 3 to receive data measured by these child units 2 by wireless communication. Each of the child units 2 has a controlling section 20 that can move to a standby state, a measuring section 21, a signal receiving section 22 to receive a measurement instructing signal from the parent unit 3, and a signal transmitting section 23 to transmit the measured data by wireless communication. The parent unit 3 has a signal transmitting section to transmit the measurement instructing signal to each of the child units 2 and a measured data receiving section 32 to receive measured data to be transmitted from the signal transmitting section 23.

摘要翻译： 提供一种无线测量装置1，其包括多个子单元2和母单元3，以通过无线通信来接收由这些子单元2测量的数据。 每个子单元2具有可以移动到待机状态的控制部分20，测量部分21，用于接收来自母单元3的测量指令信号的信号接收部分22以及信号发送部分23， 通过无线通信测量数据。 母单元3具有信号发送部分，用于将测量指示信号发送到每个子单元2和测量数据接收部分32，以接收从信号发送部分23发送的测量数据。

公开(公告)号：US6158283A

公开(公告)日：2000-12-12

申请号：US798290

申请日：1997-02-07

申请人： Masataka Shinogi ,  Yutaka Saitoh ,  Kenji Kato

发明人： Masataka Shinogi ,  Yutaka Saitoh ,  Kenji Kato

IPC分类号： G01L1/18 ,  B81B3/00 ,  B81B7/00 ,  G01L9/00 ,  G01L9/04 ,  G01P1/02 ,  G01P15/12 ,  G01P15/18 ,  H01L21/301 ,  H01L29/84

CPC分类号： B81B7/0077 ,  G01P1/023 ,  G01P15/123 ,  G01P2015/0828

摘要： A semiconductor acceleration sensor comprises a cantilever structure formed from a semiconductor wafer and having a first surface for receiving an acceleration force, a second surface disposed generally orthogonal to the first surface, and strain sensing portions disposed on the second surface. A supporting body supports the cantilever structure. A plurality of bridge circuits are disposed on the second surface of the rectangular parallelepiped shaped structure. Each of the bridge circuits has a plurality of the strain sensing portions.

摘要翻译： 半导体加速度传感器包括由半导体晶片形成并具有用于接收加速力的第一表面的悬臂结构，大致垂直于第一表面设置的第二表面和设置在第二表面上的应变感测部。 支撑体支撑悬臂结构。 多个桥接电路设置在长方体形状结构的第二表面上。 每个桥接电路具有多个应变感测部分。

公开(公告)号：US6110634A

公开(公告)日：2000-08-29

申请号：US355313

申请日：1999-07-30

申请人： Masataka Sawano ,  Taito Muraoka ,  Yutaka Saitoh ,  Hiroyoshi Yamaga ,  Rie Murakami

发明人： Masataka Sawano ,  Taito Muraoka ,  Yutaka Saitoh ,  Hiroyoshi Yamaga ,  Rie Murakami

IPC分类号： G03G9/087 ,  G03G9/097

CPC分类号： G03G9/08795 ,  G03G9/09783

摘要： The present invention relates to an electrophotographic toner containing a binder resin having an acid value in the range of from 0.1 to 50 and a novel compound of zirconium complex or salt useful as a charge control agent for the electrophotographic toner.

摘要翻译： PCT No.PCT / JP98 / 05375 Sec。 371日期1999年7月30日第 102（e）1999年7月30日PCT PCT 1998年11月30日PCT公布。 出版物WO99 /​​ 28792 日期1999年6月10日本发明涉及含有酸值在0.1-50范围内的粘合剂树脂和可用作电子照相调色剂的电荷控制剂的锆络合物或盐的新型化合物的电子照相调色剂。