公开(公告)号：US06403422B2

公开(公告)日：2002-06-11

申请号：US09197567

申请日：1998-11-23

Applicant: Hidenori Arita ,  Kazuaki Miyata

Inventor： Hidenori Arita ,  Kazuaki Miyata

IPC: H01L218236

CPC classification number: H01L27/1126 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device is provided with an element isolating region disposed in a matrix to define a channel region on a semiconductor substrate, gate interconnection layers extending in a direction and disposed at predetermined intervals from each other above element isolating region, and aluminum interconnection layers extending in a direction intersecting gate interconnection layers and disposed at predetermined intervals from each other, aluminum interconnection layer being disposed above element isolating region. Thus, it becomes possible to provide a semiconductor device and a method of manufacturing thereof which enable the reduction in time required for the final manufacturing steps of the semiconductor device after the ROM specifications are determined.

Abstract translation: 所述半导体器件设置有元件隔离区域，所述元件隔离区域设置在矩阵中以限定半导体衬底上的沟道区域，在元件隔离区域上方向延伸并以预定间隔彼此间隔设置的栅极互连层， 与门互连层相交的方向并以彼此间隔开的预定间隔布置，铝互连层设置在元件隔离区上方。 因此，可以提供一种半导体器件及其制造方法，其能够在确定ROM规格之后缩短半导体器件的最终制造步骤所需的时间。

公开(公告)号：US20120212043A1

公开(公告)日：2012-08-23

申请号：US13401205

申请日：2012-02-21

Applicant: Kazuaki MIYATA ,  Takeshi KOJIMA ,  Tomoyuki FUTAMURA

Inventor： Kazuaki MIYATA ,  Takeshi KOJIMA ,  Tomoyuki FUTAMURA

IPC: B60T13/66 ,  B60T8/1755 ,  G06F19/00

CPC classification number: B60T8/17554 ,  B60T7/042 ,  B60T13/662 ,  B60T13/686 ,  B60T2230/03

Abstract: A brake fluid pressure control apparatus for a vehicle includes a parameter calculation unit configured to calculate a rollover detection parameter; and a steering maneuver determination unit configured to determine whether an abrupt steering maneuver is made. The parameter calculation unit is configured to calculate a first composition roll angle as the rollover detection parameter, by combining at a predetermined weight assignment ratio a first roll angle equivalent to an actual roll angle with a second roll angle obtained using a parameter which changes with a phase earlier than the first roll angle, and to calculate the first composition roll angle by changing the weight assignment ratio such that a weight of the second roll angle is higher when the steering maneuver determination unit determines that an abrupt steering maneuver is made than when the steering maneuver determination unit determines that the abrupt steering maneuver is not made.

Abstract translation: 一种用于车辆的制动液压控制装置，包括：参数计算单元，被配置为计算翻转检测参数; 以及被配置为确定是否进行突然的转向操纵的转向操纵确定单元。 参数计算单元被配置为计算第一组合滚动角度作为翻转检测参数，通过以预定的重量分配比结合与实际滚动角度相等的第一滚动角度与使用以下变化的参数获得的第二滚动角度 并且通过改变重量分配比率来计算第一组合滚动角度，使得当转向操纵确定单元确定进行突然的转向操纵时第二滚动角度的重量高于当第二滚动角度的重量时 转向机动确定单元确定没有进行突然的转向操纵。

公开(公告)号：US08180543B2

公开(公告)日：2012-05-15

申请号：US12163182

申请日：2008-06-27

Applicant: Tomoyuki Futamura ,  Takeshi Kojima ,  Kazuaki Miyata

Inventor： Tomoyuki Futamura ,  Takeshi Kojima ,  Kazuaki Miyata

IPC: G06F7/70

CPC classification number: B60T8/1755 ,  B60T8/1708 ,  B60T2230/06 ,  B60T2250/06

Abstract: A movement stabilizing control ECU 25 includes a differential unit 25a, a cycle calculation unit 25b, a time constant/gain setting portion 25c, a first-order lag processing unit 25d, a pendulum movement detection unit 25e, a control amount calculation portion 25f and a control amount output unit 25g. The time constant/gain setting portion 25c sets a time constant τ and a gain K used at the time of subjecting a yaw acceleration ω′ which is a time-differential value of a yaw rate ω to the first-order lag processing at the first-order lag processing unit 25d, with reference to a function or data of a look-up table, for example, depending on the cycle or the frequency of the yaw acceleration ω′ due to the pendulum movement. The control amount calculation portion 25f multiplies the amplitude of a yaw acceleration ωd′ outputted from the first-order lag processing unit 25d by a predetermined constant to calculate a yaw control amount with a phase in opposite to that of the yaw acceleration ωd′ and outputs the yaw control amount to the control amount output unit 25g.

Abstract translation: 运动稳定控制ECU25包括差动单元25a，周期计算单元25b，时间常数/增益设定部25c，一阶滞后处理单元25d，摆动检测单元25e，控制量计算部25f和 控制量输出单元25g。 时间常数/增益设定部25c将作为偏航率ω的时差微分值的偏航加速度ω'和第一级滞后处理中使用的增益K设定为时间常数τ和增益K. 例如，根据摆动运动引起的偏航加速度ω'的周期或频率，参考查询表的功能或数据，进行时滞处理单元25d。 控制量计算部分25f将从一级滞后处理单元25d输出的横摆加速度ωd'的振幅乘以预定常数以计算与偏航加速度ωd'相反的相位的偏航控制量，并输出 到控制量输出单元25g的偏航控制量。

公开(公告)号：US5043788A

公开(公告)日：1991-08-27

申请号：US396501

申请日：1989-08-21

Applicant: Kayoko Omoto ,  Kazuaki Miyata

Inventor： Kayoko Omoto ,  Kazuaki Miyata

IPC: H01L27/06 ,  H01L27/092

CPC classification number: H01L27/0922 ,  H01L27/0623

Abstract: A single chip microcomputer as a semiconductor device comprises CMOS logic portion and a driver portion operating at a high voltage which can be connected to an external device. In the region of the CMOS logic portion, a P type well layer and an N type well layer are formed on a P type silicon substrate. An N type well layer is formed in the region constituting the driver portion. The junction depth of the N type well layer constituting the driver portion is made deeper than that of the N type well layer constituting the CMOS logic portion. A MOS transistor is formed in the region of each well layer in the CMOS logic portion. A MOS transistor whose drain breakdown voltage is increased is formed in the region of the N type well layer of the driver portion. The junction depth of the N type well layer is made deeper than that of the N type well layer constituting the CMOS logic portion at least below the drain region of this MOS transistor. The MOS transistor constituting the CMOS logic portion operates at a lower voltage while the MOS transistor constituting the driver portion operates at a higher voltage in order to drive external devices such as a fluorescent display tube connected thereto.

Abstract translation: 作为半导体器件的单片微计算机包括CMOS逻辑部分和可以连接到外部设备的高电压操作的驱动器部分。 在CMOS逻辑部分的区域中，在P型硅衬底上形成P型阱层和N型阱层。 在构成驱动器部分的区域中形成N型阱层。 构成驱动器部分的N型阱层的结深比构成CMOS逻辑部分的N型阱层的结深更深。 MOS晶体管形成在CMOS逻辑部分中的每个阱层的区域中。 漏极击穿电压增加的MOS晶体管形成在驱动器部分的N型阱层的区域中。 N型阱层的结深度比构成CMOS逻辑部分的至少在该MOS晶体管的漏极区域的N型阱层的结深更深。 构成CMOS逻辑部分的MOS晶体管在低电压下工作，而构成驱动器部分的MOS晶体管以更高的电压工作，以便驱动诸如与其连接的荧光显示管的外部器件。

公开(公告)号：US4990982A

公开(公告)日：1991-02-05

申请号：US428017

申请日：1989-10-26

Applicant: Kayoko Omoto ,  Kazuaki Miyata

Inventor： Kayoko Omoto ,  Kazuaki Miyata

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L29/78 ,  H01L29/7835

Abstract: The semiconductor device is of high break down voltage type and has a source, drain and a gate deposited therebetween on the semiconductor substrate. The gate oxide film has a thick portion and below that portion, a doped layer as a drain is provided with two layers having different impurity concentration.

Abstract translation: 半导体器件具有高击穿电压类型，并且在半导体衬底之间具有淀积在其间的源极，漏极和栅极。 栅极氧化膜具有厚的部分并且在该部分的下方，作为漏极的掺杂层具有不同杂质浓度的两层。

公开(公告)号：US20090005946A1

公开(公告)日：2009-01-01

申请号：US12163182

申请日：2008-06-27

Applicant: Tomoyuki Futamura ,  Takeshi Kojima ,  Kazuaki Miyata

Inventor： Tomoyuki Futamura ,  Takeshi Kojima ,  Kazuaki Miyata

IPC: B60T8/1755

CPC classification number: B60T8/1755 ,  B60T8/1708 ,  B60T2230/06 ,  B60T2250/06

Abstract: A movement stabilizing control ECU 25 includes a differential unit 25a, a cycle calculation unit 25b, a time constant/gain setting portion 25c, a first-order lag processing unit 25d, a pendulum movement detection unit 25e, a control amount calculation portion 25f and a control amount output unit 25g. The time constant/gain setting portion 25c sets a time constant τ and a gain K used at the time of subjecting a yaw acceleration ω′ which is a time-differential value of a yaw rate ω to the first-order lag processing at the first-order lag processing unit 25d, with reference to a function or data of a look-up table, for example, depending on the cycle or the frequency of the yaw acceleration ω′ due to the pendulum movement. The control amount calculation portion 25f multiplies the amplitude of a yaw acceleration ωd′ outputted from the first-order lag processing unit 25d by a predetermined constant to calculate a yaw control amount with a phase in opposite to that of the yaw acceleration ωd′ and outputs the yaw control amount to the control amount output unit 25g.

Abstract translation: 运动稳定控制ECU25包括差动单元25a，周期计算单元25b，时间常数/增益设定部25c，一阶滞后处理单元25d，摆动检测单元25e，控制量计算部25f和 控制量输出单元25g。 时间常数/增益设定部分25c将作为第一级滞后处理的偏航率ω的时间差值的偏航加速度ω''所使用的时间常数τ和增益K设定为第一阶滞后处理 例如，根据由摆锤运动引起的偏航加速度ω''的周期或频率，参考查询表的功能或数据， - 阶滞后处理单元25d。 控制量计算部分25f将从一级滞后处理单元25d输出的偏航加速度ωgad'的振幅乘以预定常数以计算与偏航加速度ωgad'相反的相位的偏航控制量，并且输出 到控制量输出单元25g的偏航控制量。

公开(公告)号：US5327000A

公开(公告)日：1994-07-05

申请号：US913683

申请日：1992-07-14

Applicant: Kazuaki Miyata ,  Masayuki Masuda

Inventor： Kazuaki Miyata ,  Masayuki Masuda

IPC: H01L27/06 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L27/02 ,  H01L29/10

CPC classification number: H01L27/088

Abstract: In a MOS type LSI comprising an n channel-open-drain-transistor capable of connecting with an analog IC driven by a high voltage, a surge breakdown voltage and a drain breakdown voltage of the open-drain-transistor is increased, and hence the reliability is increased. An n channel-open-drain-transistor includes a ring-shaped gate electrode and a drain region. A drain region is surrounded by a gate electrode. Drain region includes an n.sup.- region and an n.sup.+ region. An n channel MOS transistor includes a gate electrode and a drain region. Drain region includes an n.sup.- region and an n.sup.+ region. An impurity concentration of n.sup.- drain region of the n channel-open-drain-transistor is higher than an impurity concentration of n.sup.- drain region of the n channel MOS transistor.

Abstract translation: 在包括能够与由高电压驱动的模拟IC连接的n沟道开路漏极晶体管的MOS型LSI中，漏极 - 漏极 - 晶体管的浪涌击穿电压和漏极击穿电压增加，因此， 可靠性提高。 n沟道开路漏极晶体管包括环形栅极电极和漏极区域。 漏极区域被栅电极包围。 漏区包括n区和n +区。 n沟道MOS晶体管包括栅极电极和漏极区域。 漏区包括n区和n +区。 n沟道开漏晶体管的n沟道区的杂质浓度高于n沟道MOS晶体管的n沟道区的杂质浓度。

公开(公告)号：US5183773A

公开(公告)日：1993-02-02

申请号：US817190

申请日：1992-01-06

Applicant: Kazuaki Miyata

Inventor： Kazuaki Miyata

IPC: H01L21/8247 ,  H01L27/02 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/0251 ,  H01L27/105 ,  H01L27/11546

Abstract: Disclosed is a structure of a semiconductor device in which an internal circuit including a memory device and a transistor having an LDD structure and an input protection device for protecting the internal circuit are formed on one semiconductor substrate, and a method of manufacturing such a semiconductor device. The input protection device and the memory device are formed at the same time. The input protection device as well as the memory device includes source/drain regions formed of high concentration inpurity regions and formed in the surface of the semiconductor substrate, and a gate electrode formed of a plurality of conductor films and formed on the surface of the semiconductor substrate between the source/drain regions. When an abnormal voltage is applied to an interconnection for supplying an electrical signal to the internal circuit, a charge flows from the interconnection through one source/drain region of the input protection device into the semiconductor substrate, so that the internal circuit is protected against an excessive charge.

Abstract translation: 公开了一种半导体器件的结构，其中在一个半导体衬底上形成有包括存储器件和具有LDD结构的晶体管和用于保护内部电路的输入保护器件的内部电路的结构，以及制造这种半导体器件的方法 。 输入保护装置和存储装置同时形成。 输入保护器件以及存储器件包括由高浓度不纯度区域形成并形成在半导体衬底的表面中的源极/漏极区域以及形成在半导体衬底的表面上的多个导体膜形成的栅电极 源/漏区之间的衬底。 当异常电压施加到用于向内部电路提供电信号的互连线时，电荷从互连通过输入保护器件的一个源极/漏极区域流入半导体衬底，使得内部电路受到保护 过量收费

公开(公告)号：US5144389A

公开(公告)日：1992-09-01

申请号：US583384

申请日：1990-09-17

Applicant: Mitsuyoshi Nakamura ,  Kazuaki Miyata

Inventor： Mitsuyoshi Nakamura ,  Kazuaki Miyata

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/7835 ,  H01L29/0626

Abstract: An MIS FET has an off-set gate structure in which a gate electrode and a drain region. The drain region is formed of an n type impurity region of a high concentration and has a pn junction region provided between the drain region and the p type silicon substrate. Further, n type impurity regions of the low concentration are in contact with a part of a peripheral portion of the n type impurity regions of the high concentration. The n type impurity regions of the low concentration alleviate the concentration of the electric field near the drain region to increase the drain breakdown voltage. The pn junction region of the n type impurity region of the high concentration and the p type silicon substrate increases a junction capacitance of the entire drain region, increases a surge current discharged to the substrate side from the drain region for the surge breakdown to increase the surge withstanding amount.

Abstract translation: MIS FET具有栅极电极和漏极区域的偏置栅极结构。 漏极区域由高浓度的n型杂质区域形成，并且在漏极区域和p型硅衬底之间具有pn结区域。 此外，低浓度的n型杂质区域与高浓度的n型杂质区域的周边部分的一部分接触。 低浓度的n型杂质区域减小了漏极区域附近的电场浓度，从而提高了漏极击穿电压。 高浓度的n型杂质区域的pn结区域和p型硅衬底增加了整个漏极区域的结电容，从而从浪涌击穿的漏极区域增加了从衬底侧排出的浪涌电流，从而增加了 浪费的金额。

公开(公告)号：US5142345A

公开(公告)日：1992-08-25

申请号：US746187

申请日：1991-08-15

Applicant: Kazuaki Miyata

Inventor： Kazuaki Miyata

IPC: H01L21/8247 ,  H01L27/02 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/0251 ,  H01L27/105 ,  H01L27/11546

Abstract: Disclosed is a structure of a semiconductor device in which an internal circuit including a memory device and a transistor having an LDD structure, and an input protection device for protecting the internal circuit are formed on one semiconductor substrate, and a method of manufacturing such a semiconductor device. The input protection device and the memory device are formed at the same time. The input protection device as well as the memory device includes source/drain regions formed of high concentration impurity regions and formed in the surface of the semiconductor substrate, and a gate electrode formed of a plurality of conductor films and formed on the surface of the semiconductor substrate between the source/drain regions. When an abnormal voltage is applied to an interconnection for supplying an electrical signal to the internal circuit, a charge flows from the interconnection through one source/drain region of the input protection device into the semiconductor substrate, so that the internal circuit is protected against an excessive charge.

Abstract translation: 公开了一种半导体器件的结构，其中在一个半导体衬底上形成有包括存储器件和具有LDD结构的晶体管的内部电路和用于保护内部电路的输入保护器件，以及制造这种半导体 设备。 输入保护装置和存储装置同时形成。 输入保护器件以及存储器件包括由高浓度杂质区形成并形成在半导体衬底的表面中的源极/漏极区域以及形成在半导体衬底的表面上的多个导体膜形成的栅电极 源/漏区之间的衬底。 当异常电压施加到用于向内部电路提供电信号的互连线时，电荷从互连通过输入保护器件的一个源极/漏极区域流入半导体衬底，使得内部电路受到保护 过量收费