公开(公告)号：US07190593B2

公开(公告)日：2007-03-13

申请号：US10022732

申请日：2001-12-20

申请人： Kiyoshi Aiki ,  Kazunori Hikone ,  Hiroyuki Adachi ,  Masayoshi Okamoto ,  Masao Onose ,  Yuji Mizuno

发明人： Kiyoshi Aiki ,  Kazunori Hikone ,  Hiroyuki Adachi ,  Masayoshi Okamoto ,  Masao Onose ,  Yuji Mizuno

IPC分类号： H05K7/10 ,  H05K7/12

CPC分类号： H01L22/32 ,  G01R31/2884 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2924/01039 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor integrated circuit device is provided in which (i) inspection pads are arranged along one side or two opposite sides of the semiconductor integrated circuit device for bonding pads arranged along the sides other than the side or the two opposite sides and (ii) the bonding pads are connected to their respective inspection pads by connection wires The inspection is carried out by applying probe needles to the pads (inspection pads and bonding pads) arranged only along one side or two opposite sides of the semiconductor integrated circuit device. The invention also provides a semiconductor integrated circuit package with leads on four sides includes a semiconductor integrated circuit device with bonding pads laid along one pair of opposite sides of the four sides, and a table for supporting the semiconductor integrated circuit device. While the bonding pads along the pair of opposite sides of the semiconductor integrated circuit device are connected with leads along the four sides of the package, and some leads are bent toward the respective pads. The present invention the inspection of a plurality of semiconductor integrated circuit devices with probe needles at a time.

摘要翻译： 提供了一种半导体集成电路器件，其中（i）检查焊盘沿着半导体集成电路器件的一侧或两个相对侧布置，用于沿着除了侧面或两个相对侧之外的侧面布置的焊盘，以及（ii） 接合焊盘通过连接线连接到它们各自的检查焊盘。通过将探针施加到仅沿着半导体集成电路器件的一侧或两个相对侧布置的焊盘（检查焊盘和焊盘）来进行检查。 本发明还提供了一种半导体集成电路封装，其四边具有引线，包括具有沿四个侧面的一对相对侧布置的接合焊盘的半导体集成电路器件，以及用于支撑半导体集成电路器件的工作台。 虽然沿着半导体集成电路器件的这对相对侧的接合焊盘沿着封装的四边与引线连接，并且一些引线朝着相应的焊盘弯曲。 本发明一次检测具有探针的多个半导体集成电路器件。

公开(公告)号：US07626498B2

公开(公告)日：2009-12-01

申请号：US11208632

申请日：2005-08-23

申请人： Kiyoshi Aiki ,  Hiroyuki Kuriyama ,  Shunzo Yamashita ,  Takanori Shimura

发明人： Kiyoshi Aiki ,  Hiroyuki Kuriyama ,  Shunzo Yamashita ,  Takanori Shimura

IPC分类号： G08B1/08

CPC分类号： H01Q1/273 ,  H01Q9/0485

摘要： To secure a stable radio-communication performance in a sensor node, the sensor node with a radio-communication circuit and a sensor, for transmitting data measured by the sensor through radio-communication, includes a first board BO2 on which an antenna ANT1 connected to the radio-communication circuit is placed, a case CASE1 containing the first board BO2, and a band that is attached to the case CASE1 so as to fix the case CASE1 to the skin. The antenna ANT1 is placed in an upper portion of the case CASE1, which corresponds to a 12 o'clock direction of a wristwatch.

摘要翻译： 为了确保传感器节点中的稳定的无线电通信性能，具有用于通过无线电通信传输由传感器测量的数据的无线电通信电路和传感器的传感器节点包括第一板B02，其上连接有天线ANT1 放置无线电通信电路，包含第一板BO2的壳体CASE1和附接到壳体CASE1的带，以将壳体CASE1固定到皮肤上。 天线ANT1被放置在壳体CASE1的上部，其对应于手表的12点钟方向。

公开(公告)号：US20060229520A1

公开(公告)日：2006-10-12

申请号：US11210740

申请日：2005-08-25

申请人： Shunzo Yamashita ,  Hiroyuki Kuriyama ,  Kiyoshi Aiki ,  Takanori Shimura

发明人： Shunzo Yamashita ,  Hiroyuki Kuriyama ,  Kiyoshi Aiki ,  Takanori Shimura

IPC分类号： A61B5/02

CPC分类号： A61B5/0002 ,  A61B5/02438 ,  A61B5/681 ,  A61B2560/0209

摘要： The precision of measuring biometric information is enhanced while suppressing the consumption of a battery in a sensor node. In a method of measuring the biometric information in a sensor node including a controller for driving a sensor to measure biometric information, the controller supplies power from a battery to an acceleration sensor for detecting the movement of a living body to detect the movement of the living body, the controller determines whether or not measurement by a pulsebeat sensor is possible based on the detected movement of the living body (P330), and shuts off power to the acceleration sensor having a power consumption lower than that of the pulsebeat sensor when the determination results show that measurement is possible, and thereafter supplying power to the pulsebeat sensor having a power consumption larger than that of the acceleration sensor to measure the biometric information (P340).

摘要翻译： 在抑制传感器节点中的电池消耗的同时增强了测量生物信息的精度。 在测量包括用于驱动传感器以测量生物特征信息的控制器的传感器节点中的生物信息的方法中，控制器将电力从电池供给到加速度传感器，用于检测活体的运动以检测生物的移动 控制器基于检测到的活体的移动来确定是否可以通过脉搏波传感器进行测量（P 330），并且在功率消耗低于脉冲波形传感器的功率消耗的加速度传感器时切断电力 确定结果表明测量是可能的，然后向具有大于加速度传感器功率消耗的脉冲波形传感器供电以测量生物特征信息（P 340）。

公开(公告)号：USRE36751E

公开(公告)日：2000-06-27

申请号：US430802

申请日：1995-04-26

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

IPC分类号： H04J3/24 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04Q11/0478 ,  H04J3/247 ,  H04L12/5601 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/256 ,  H04L49/3081 ,  H04L2012/5627 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5681

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元 训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。 开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配 以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。 缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元 表装置。

公开(公告)号：US5799014A

公开(公告)日：1998-08-25

申请号：US306978

申请日：1994-09-16

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

IPC分类号： H04J3/24 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

公开(公告)号：US08330596B2

公开(公告)日：2012-12-11

申请号：US12155457

申请日：2008-06-04

申请人： Takeshi Tanaka ,  Shunzo Yamashita ,  Kiyoshi Aiki

发明人： Takeshi Tanaka ,  Shunzo Yamashita ,  Kiyoshi Aiki

IPC分类号： G08B1/08

CPC分类号： A61B5/0002 ,  A61B5/02438 ,  A61B5/11 ,  A61B5/7232 ,  A61B2560/045 ,  A61B2562/0219 ,  H04W84/18

摘要： Provided is a sensor node including: a sensor for measuring biological information; a CPU for acquiring data by driving the sensor; a wireless communication unit for transmitting the data acquired by the CPU; a battery for supplying the control unit, the wireless communication unit, and the sensor with electric power; a RAM for storing the data; a compression unit for compressing the data stored in the RAM when the wireless communication unit cannot carry out the transmission; and a flash memory for storing the compressed data, thereby storing as much sensing data as possible on the sensor node, which is limited in resources, and preventing loss of the sensing data.

摘要翻译： 提供了一种传感器节点，包括：用于测量生物信息的传感器; 用于通过驱动传感器来获取数据的CPU; 用于发送由CPU获取的数据的无线通信单元; 用于向控制单元，无线通信单元和传感器供电的电池; 用于存储数据的RAM; 压缩单元，用于在无线通信单元不能进行发送时压缩存储在RAM中的数据; 以及用于存储压缩数据的闪速存储器，从而在传感器节点上存储尽可能多的感测数据，其在资源上受到限制，并且防止感测数据的丢失。

公开(公告)号：US20060076934A1

公开(公告)日：2006-04-13

申请号：US11072490

申请日：2005-03-07

申请人： Yuji Ogata ,  Shunzo Yamashita ,  Takanori Shimura ,  Kiyoshi Aiki

发明人： Yuji Ogata ,  Shunzo Yamashita ,  Takanori Shimura ,  Kiyoshi Aiki

IPC分类号： H02J7/00

CPC分类号： H02J7/0031

摘要： In a sensor node SN driven by a secondary battery, a charge/discharge control circuit can be realized and an unnecessary circuit in the sensor node can be eliminated for its miniaturization. The charge/discharge control circuit and the sensor node have a comparator for monitoring a battery voltage, a control circuit for converting an output of the comparator into an interrupt signal, a micro controller for performing charge/discharge control only when detecting the interrupt signal, and a switch turned ON or OFF under control of the micro controller. When the battery voltage is not lower than a first predetermined voltage, the switch is turned OFF to thereby stop charging operation. When the battery voltage is not higher than a second predetermined voltage, the switch is turned OFF to stop discharging operation. A circuit necessary in a charge mode is provided in a charger side.

摘要翻译： 在由二次电池驱动的传感器节点SN中，可以实现充放电控制电路，并且可以消除传感器节点中的不必要的电路以使其小型化。 充放电控制电路和传感器节点具有用于监视电池电压的比较器，用于将比较器的输出转换为中断信号的控制电路，仅在检测到中断信号时执行充放电控制的微控制器， 并且在微控制器的控制下开关被接通或断开。 当电池电压不低于第一预定电压时，开关断开，从而停止充电操作。 当电池电压不高于第二预定电压时，开关断开以停止放电操作。 在充电器侧提供充电模式所需的电路。

公开(公告)号：US06463057B1

公开(公告)日：2002-10-08

申请号：US09714947

申请日：2000-11-20

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

IPC分类号： H04L1256

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682 ,  H04Q11/0478

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元 训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。 开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配 以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。 缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元 表装置。

公开(公告)号：US06396831B1

公开(公告)日：2002-05-28

申请号：US09715104

申请日：2000-11-20

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

IPC分类号： H04L1256

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682 ,  H04Q11/0478

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

公开(公告)号：US06339596B1

公开(公告)日：2002-01-15

申请号：US08906909

申请日：1997-08-06

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

IPC分类号： H04L1256

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682 ,  H04Q11/0478

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.