公开(公告)号：US07265369B2

公开(公告)日：2007-09-04

申请号：US10250559

申请日：2002-01-17

申请人： Kazuyuki Maruo

发明人： Kazuyuki Maruo

IPC分类号： G01J1/00 ,  G01J5/02

CPC分类号： G01N21/552

摘要： A chemical detecting apparatus includes a substrate 10 for chemicals in gas-to-be-monitored to be adsorbed to, a substrate adsorption rate improving means 12 which enhances the adsorption of the chemical in the gas-to-be-monitored to the substrate, an infrared light source 20 which applies an infrared light to the substrate 10 with the chemical adsorbed to, and an infrared light detector 22 which detects the infrared light which has made multiple reflections in the substrate 10 and exited the substrate. Thus, chemicals present in environments can be detected at high speed and with high sensitivity.

摘要翻译： 一种化学检测装置包括：用于吸附气体的待化学物质的基板10;基板吸附率提高装置12，其增强待监测的气体中的化学物质对基板的吸附; 红外光源20，其将吸收有化学物质的红外光施加到基板10;以及红外光检测器22，其检测在基板10中进行多次反射并离开基板的红外光。 因此，可以以高速和高灵敏度检测环境中存在的化学物质。

公开(公告)号：US20060017071A1

公开(公告)日：2006-01-26

申请号：US11182018

申请日：2005-07-15

申请人： Tadahiro Ohmi ,  Koji Kotani ,  Kazuyuki Maruo ,  Takahiro Yamaguchi

发明人： Tadahiro Ohmi ,  Koji Kotani ,  Kazuyuki Maruo ,  Takahiro Yamaguchi

IPC分类号： H01L29/76

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/11807

摘要： There is provided a high-performance semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a switch block for switching connections among a plurality of signal lines by means of a plurality of transistors formed respectively in a plurality of semiconductor layers and a plurality of logic blocks formed in each of the plurality of semiconductor layers and connected to each of the plurality of signal lines. The first switch block is a programmable switch block capable of changing the connection topology among the plurality of signal lines.

摘要翻译： 提供了电路面积小，布线长度短的高性能半导体集成电路。 半导体集成电路构造成多层结构，并且设置有用于通过分别形成在多个半导体层中的多个晶体管和多个形成的多个逻辑块来在多个信号线之间切换连接的开关块 在多个半导体层的每一个中并连接到多个信号线中的每一个。 第一开关块是能够改变多个信号线之间的连接拓扑的可编程开关块。

公开(公告)号：US06408105B1

公开(公告)日：2002-06-18

申请号：US09310789

申请日：1999-05-12

申请人： Kazuyuki Maruo

发明人： Kazuyuki Maruo

IPC分类号： G06K936

CPC分类号： G06T7/001 ,  G06T7/13 ,  G06T7/168 ,  G06T7/70 ,  G06T2207/10056 ,  G06T2207/20061 ,  G06T2207/30141 ,  G06T2207/30148

摘要： Image data is edge-processed and then digitized. This image data is Hough-transformed to generate a parameter plane in which multiple Hough-curves are plotted in a parameter space, from which coordinates with multiple intersected Hough-curves are extracted and grouped. For each group, representative coordinates are selected to estimate slopes of linear components in the image data. In this way, the linear components can be recognized from the image data to estimate the slope, thereby making it possible to modify slopes of linear components in image data of a semiconductor wafer taken at an arbitrary angle or the like.

摘要翻译： 图像数据进行边缘处理，然后数字化。 该图像数据被霍夫变换以生成参数平面，其中在参数空间中绘制多个霍夫曲线，从中提取并分组具有多个相交霍夫曲线的坐标。 对于每个组，选择代表坐标来估计图像数据中的线性分量的斜率。 以这种方式，可以从图像数据中识别线性​​分量以估计斜率，从而可以修改以任意角度等拍摄的半导体晶片的图像数据中的线性分量的斜率。

公开(公告)号：US6081163A

公开(公告)日：2000-06-27

申请号：US234979

申请日：1999-01-22

申请人： Hitoshi Ujiie ,  Kazuyuki Maruo

发明人： Hitoshi Ujiie ,  Kazuyuki Maruo

IPC分类号： G04G3/02 ,  G04G7/02 ,  H03L1/02 ,  H03L7/085 ,  H03L7/14 ,  H03L7/18 ,  H03L7/07

CPC分类号： G01S19/235 ,  G04G3/022 ,  G04R40/02 ,  G04R40/06 ,  H03L7/085 ,  H03L7/146 ,  H03L7/18 ,  H03L1/022

摘要： A frequency standard generator includes a voltage controlled crystal oscillator (VCXO) for generating high stability output signal, a radio wave receiver to receive a radio wave which includes a high accuracy reference time signal, a time interval measuring circuit which measures a phase difference between the reference time signal and the output signal of the VCXO; a frequency control processor which determines control data based on the phase difference data to phase lock the output signal of the VCXO to the reference time signal, a frequency deviation data generator for compiling the phase difference data to obtain frequency deviation trend data of the VCXO, and a compensation data generator for generating compensation data based on the frequency deviation trend data to compensate frequency changes in said VCXO when the reference time signal is unavailable.

摘要翻译： 频率标准发生器包括用于产生高稳定度输出信号的电压控制晶体振荡器（VCXO），用于接收包括高精度基准时间信号的无线电波的无线电波接收器，测量第二相位差之间的相位差的时间间隔测量电路 参考时间信号和VCXO的输出信号; 频率控制处理器，其基于相位差数据确定控制数据，以将VCXO的输出信号锁定到参考时间信号;频率偏差数据发生器，用于编译相位差数据以获得VCXO的频率偏差趋势数据; 以及补偿数据发生器，用于基于频率偏差趋势数据产生补偿数据，以补偿当基准时间信号不可用时所述VCXO中的频率变化。

公开(公告)号：US5963661A

公开(公告)日：1999-10-05

申请号：US987257

申请日：1997-12-09

申请人： Haruo Kato ,  Kazuyuki Maruo

发明人： Haruo Kato ,  Kazuyuki Maruo

IPC分类号： G01N21/88 ,  G01N21/94 ,  G01N21/956 ,  G06T1/00 ,  G06T7/00 ,  G06T7/60 ,  G06K9/00

CPC分类号： G06T7/0004 ,  G06T7/0042 ,  G06T2207/20056 ,  G06T2207/30141 ,  G06T2207/30148

摘要： A particle-like point in an image is detected to detect a defect by directly processing an image of an object to be inspected. The image is first binarized, and the binarized image is scanned along an X-axis or a Y-axis, and a particle-like point in the image is approximated by a rectangular area. Information representative of the coordinates of the center of the rectangular area and the size of the rectangular area is outputted as information of the detected particle-like point.

摘要翻译： 通过直接处理待检查对象的图像来检测图像中的粒子点以检测缺陷。 图像首先被二值化，并且沿着X轴或Y轴扫描二值化图像，并且图像中的粒子像点由矩形区域近似。 输出表示矩形区域的中心坐标和矩形区域的尺寸的信息作为检测到的粒子点的信息。

公开(公告)号：US20080318370A1

公开(公告)日：2008-12-25

申请号：US12110800

申请日：2008-04-28

申请人： Tadahiro Ohmi ,  Koji Kotani ,  Kazuyuki Maruo ,  Takahiro Yamaguchi

发明人： Tadahiro Ohmi ,  Koji Kotani ,  Kazuyuki Maruo ,  Takahiro Yamaguchi

IPC分类号： H01L21/336

CPC分类号： H01L27/12 ,  H01L21/8221 ,  H01L27/0688 ,  Y10S257/903

摘要： There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring layer which is deposited on the first semiconductor layer and in which metal wires are formed, a second semiconductor layer deposited on the wiring layer and a second semiconductor layer transistor formed in the second semiconductor layer. It is noted that insulation of a gate insulating film of the first semiconductor layer transistor is almost equal with that of a gate insulating film of the second semiconductor layer transistor and the gate insulating film of the second semiconductor layer transistor is formed by means of radical oxidation or radical nitridation.

摘要翻译： 提供电路面积小，布线长度短的小型半导体集成电路。 半导体集成电路构造为多层结构，并且设置有第一半导体层，形成在第一半导体层中的第一半导体层晶体管，布置在第一半导体层上并且其中金属线为 形成，沉积在布线层上的第二半导体层和形成在第二半导体层中的第二半导体层晶体管。 注意，第一半导体层晶体管的栅极绝缘膜的绝缘几乎等于第二半导体层晶体管的栅极绝缘膜的绝缘，并且通过自由基氧化形成第二半导体层晶体管的栅极绝缘膜 或自由基氮化。

公开(公告)号：US07193434B2

公开(公告)日：2007-03-20

申请号：US11182018

申请日：2005-07-15

申请人： Tadahiro Ohmi ,  Koji Kotani ,  Kazuyuki Maruo ,  Takahiro Yamaguchi

发明人： Tadahiro Ohmi ,  Koji Kotani ,  Kazuyuki Maruo ,  Takahiro Yamaguchi

IPC分类号： H03K19/173

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/11807

摘要： There is provided a high-performance semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a switch block for switching connections among a plurality of signal lines by means of a plurality of transistors formed respectively in a plurality of semiconductor layers and a plurality of logic blocks formed in each of the plurality of semiconductor layers and connected to each of the plurality of signal lines. The first switch block is a programmable switch block capable of changing the connection topology among the plurality of signal lines.

摘要翻译： 提供了电路面积小，布线长度短的高性能半导体集成电路。 半导体集成电路构造成多层结构，并且设置有用于通过分别形成在多个半导体层中的多个晶体管和多个形成的多个逻辑块来在多个信号线之间切换连接的开关块 在多个半导体层的每一个中并连接到多个信号线中的每一个。 第一开关块是能够改变多个信号线之间的连接拓扑的可编程开关块。

公开(公告)号：US20060184600A1

公开(公告)日：2006-08-17

申请号：US11340870

申请日：2006-01-27

申请人： Kazuyuki Maruo ,  Takahiro Yamaguchi

发明人： Kazuyuki Maruo ,  Takahiro Yamaguchi

IPC分类号： G06F7/38

CPC分类号： G06F7/729

摘要： There is provided a scaling operator for calculating a quotient in a first residue format obtained by dividing an input number in the first residue format by a second modulus in a residue number system for representing numbers by the first residue format of a set of residues obtained with respect to first modulus and residues obtained with respect to second modulus, having a subtracter for outputting inter-moduli values of difference which are values of difference between the residues obtained with respect to the first modulus and the residues obtained with respect to the second modulus and a quotient outputting section for outputting a set of residues of the quotient obtained with respect to the first modulus and residues of the quotient obtained with respect to the second modulus as the quotient based on the inter-moduli values of difference.

摘要翻译： 提供了一种缩放算子，用于计算第一残差格式的商，其通过将第一残差格式中的输入数除以残差数系统中的第二模数，用于表示数字，该第一残差格式是通过以 相对于第二模量获得的第一模量和残余物，具有用于输出差异值的减法器，该减法器是相对于第一模量获得的残差与相对于第二模数获得的残差之间的差的值， 商商输出部分，用于输出相对于第二模数获得的关于第二模数获得的商的残差的一组残差，作为商的差分模值，作为商。

公开(公告)号：US06647406B1

公开(公告)日：2003-11-11

申请号：US09444721

申请日：1999-11-24

申请人： Kazuyuki Maruo ,  Tadashi Shibata

发明人： Kazuyuki Maruo ,  Tadashi Shibata

IPC分类号： G06G7164

CPC分类号： G06G7/22 ,  G06G7/14

摘要： A sum of product circuit (20) which adds up two input voltages, each of which is multiplied by the prescribed coefficients. The sum of product circuit (20) has a &ngr; MOS transistor (50), a first and a second capacitance (C1, C2), and an output terminal (86). The &ngr; MOS transistor (50) includes a drain (70), source (72), and a floating gate (74). The first and a second capacitance (C1, C2) connects each of two input voltages to the floating gate (74) by capacity coupling. The output terminal (86) outputs a voltage realized between a resister element (R0) and the &ngr; MOS transistor (50). A constant voltage is applied between the drain (70) and the source (72) through the resister element (R0).

摘要翻译： 产生电路（20）的总和将两个输入电压相加，每个输入电压乘以规定的系数。 产品电路（20）的总和具有nu MOS晶体管（50），第一和第二电容（C1，C2）和输出端子（86）。 nu MOS晶体管（50）包括漏极（70），源极（72）和浮动栅极（74）。 第一和第二电容（C1，C2）通过电容耦合将两个输入电压中的每一个连接到浮置栅极（74）。 输出端子（86）输出在电阻元件（R0）和nuMOS晶体管（50）之间实现的电压。 通过电阻元件（R0）在漏极（70）和源极（72）之间施加恒定的电压。

公开(公告)号：US06584236B1

公开(公告)日：2003-06-24

申请号：US09413818

申请日：1999-10-07

申请人： Kazuyuki Maruo ,  Takahiro Yamaguchi ,  Masayoshi Ichikawa

发明人： Kazuyuki Maruo ,  Takahiro Yamaguchi ,  Masayoshi Ichikawa

IPC分类号： A06K932

CPC分类号： G06T7/0004 ,  G06T7/73 ,  G06T2207/10061 ,  G06T2207/30141 ,  G06T2207/30148

摘要： An image processing apparatus for detecting the inclination of an object is provided. This image processing apparatus has a read means which reads the object and outputs image data, an amount of change calculation means which calculates the sum of the amounts of change of the image data of the object in at least one direction, and an inclination calculation means which calculates the inclination of the object based on the sum calculated by the amount of change calculation means.

摘要翻译： 提供了一种用于检测物体的倾斜度的图像处理装置。 该图像处理装置具有读取对象并输出图像数据的读取装置，改变计算装置，其计算至少一个方向上的对象的图像数据的变化量之和和倾斜计算装置 其基于由变化量计算装置计算的总和来计算物体的倾斜度。