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1.发明授权公开(公告)号：US08551853B2
公开(公告)日：2013-10-08
申请号：US13498541
申请日：2011-07-07
申请人： Kiyotaka Tsuji , Takumi Mikawa , Kenji Tominaga
发明人： Kiyotaka Tsuji , Takumi Mikawa , Kenji Tominaga
IPC分类号： H01L21/20
CPC分类号： H01L27/2463 , H01L21/76879 , H01L45/04 , H01L45/146 , H01L45/1683
摘要： A non-volatile semiconductor memory device comprises a plurality of memory cell holes (101) formed through an interlayer insulating layer (80) at respective cross-points of a plurality of first wires (10) of a stripe shape and a plurality of second wires (20) of a stripe shape when viewed from above such that the memory cell holes (101) expose upper surfaces of the plurality of first wires, respectively, a plurality of dummy holes (111) formed on the plurality of first wires in the interlayer insulating layer such that the dummy holes reach the upper surfaces of the plurality of first wires, respectively, and stacked-layer structures formed inside the memory cell holes and inside the dummy holes, respectively, each of the stacked-layer structures including a first electrode (30) and a variable resistance layer (40); an area of a portion of the first wire which is exposed in a lower opening of one of the dummy holes being greater than an area of a portion of the first wire which is exposed in a lower opening of one of the memory cell holes; and one or more of the dummy holes being formed on each of the first wires.
摘要翻译： 一种非易失性半导体存储器件包括：多条存储单元孔（101），其形成在层状绝缘层（80）的多个第一布线（10）的条状形状的各个交叉点处，多个第二布线 （101）分别暴露在所述多个第一布线的上表面的多个虚设孔（111），所述多个第一布线形成在所述中间层 绝缘层，使得所述虚拟孔分别到达所述多个第一布线的上表面，分别形成在所述存储单元孔内部和所述虚拟孔内部的堆叠层结构，所述层叠层结构中的每一个包括第一电极 （30）和可变电阻层（40）; 在一个虚拟孔的下部开口中露出的第一线的一部分的面积大于暴露在一个存储单元孔的下部开口中的第一线的一部分的面积; 并且在每个第一导线上形成一个或多个虚拟孔。
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公开(公告)号：US08394669B2
公开(公告)日：2013-03-12
申请号：US13128575
申请日：2010-07-12
申请人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
发明人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
CPC分类号： H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1666 , H01L45/1675
摘要： A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.
摘要翻译： 在根据本发明的通孔交叉点结构存储装置中使用的电阻可变元件（100）和包括电阻可变元件的电阻变化存储装置包括基板（7）和层间绝缘层（ 3），并且具有形成贯通层间绝缘层的通孔（4）的构造，在通孔的外侧形成有包含过渡金属氧化物的第一电阻变化层（2）， 在通孔内形成有包含过渡金属氧化物的第二电阻变化层（5），第一电阻变化层的电阻率与第二电阻变化层不同，第一电阻变化层和第二电阻变化层接触 彼此仅在更靠近基板的通孔的开口（20）中。
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3.发明申请公开(公告)号：US20120181500A1
公开(公告)日：2012-07-19
申请号：US13498541
申请日：2011-07-07
申请人： Kiyotaka Tsuji , Takumi Mikawa , Kenji Tominaga
发明人： Kiyotaka Tsuji , Takumi Mikawa , Kenji Tominaga
CPC分类号： H01L27/2463 , H01L21/76879 , H01L45/04 , H01L45/146 , H01L45/1683
摘要： A non-volatile semiconductor memory device comprises a plurality of memory cell holes (101) formed through an interlayer insulating layer (80) at respective cross-points of a plurality of first wires (10) of a stripe shape and a plurality of second wires (20) of a stripe shape when viewed from above such that the memory cell holes (101) expose upper surfaces of the plurality of first wires, respectively, a plurality of dummy holes (111) formed on the plurality of first wires in the interlayer insulating layer such that the dummy holes reach the upper surfaces of the plurality of first wires, respectively, and stacked-layer structures formed inside the memory cell holes and inside the dummy holes, respectively, each of the stacked-layer structures including a first electrode (30) and a variable resistance layer (40); an area of a portion of the first wire which is exposed in a lower opening of one of the dummy holes being greater than an area of a portion of the first wire which is exposed in a lower opening of one of the memory cell holes; and one or more of the dummy holes being formed on each of the first wires.
摘要翻译： 一种非易失性半导体存储器件包括：多条存储单元孔（101），其形成在层状绝缘层（80）的多个第一布线（10）的条状形状的各个交叉点处，多个第二布线 （101）分别暴露在所述多个第一布线的上表面的多个虚设孔（111），所述多个第一布线形成在所述中间层 绝缘层，使得所述虚拟孔分别到达所述多个第一布线的上表面，分别形成在所述存储单元孔内部和所述虚拟孔内部的堆叠层结构，所述层叠层结构中的每一个包括第一电极 （30）和可变电阻层（40）; 在一个虚拟孔的下部开口中露出的第一线的一部分的面积大于暴露在一个存储单元孔的下部开口中的第一线的一部分的面积; 并且在每个第一导线上形成一个或多个虚拟孔。
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公开(公告)号：US20100264393A1
公开(公告)日：2010-10-21
申请号：US12747060
申请日：2008-12-02
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A nonvolatile memory device of the present invention comprises a substrate (1), first wires (3), first filling constituents (5) filled into first through-holes (4), respectively, second wires (11) which cross the first wires (3) perpendicularly to the first wires (3), respectively, each of the second wires (11) including a plurality of layers including a resistance variable layer (6) of each of first resistance variable elements, a conductive layer (7) and a resistance variable layer (8) of each of second resistance variable elements which are stacked together in this order, second filling constituents (14) filled into second through-holes (13), respectively, and third wires (15), and the conductive layer (7) of the second wires (11) serves as the electrodes of the first resistance variable elements (9) and the electrodes of the second resistance variable elements (10).
摘要翻译： 本发明的非易失性存储装置包括基板（1），第一布线（3），分别填充到第一通孔（4）中的第一填充构件（5），分别穿过第一布线 3）分别垂直于第一导线（3），每个第二导线（11）包括多个层，包括第一电阻可变元件中的每一个的电阻变化层（6），导电层（7）和 按顺序堆叠在一起的第二电阻可变元件的电阻变化层（8），分别填充到第二通孔（13）中的第二填充组分（14）和第三导线（15），以及导电层 第二电线（11）的电极（7）用作第一电阻可变元件（9）的电极和第二电阻可变元件（10）的电极。
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公开(公告)号：USD335930S
公开(公告)日：1993-05-25
申请号：US709445
申请日：1991-06-03
申请人： Kenji Tominaga
设计人： Kenji Tominaga
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公开(公告)号：US5087408A
公开(公告)日：1992-02-11
申请号：US567950
申请日：1990-08-15
申请人： Kenji Tominaga , Minoru Miki , Tooru Takahashi , Tetsuo Horiuchi , Hideo Morishima , Takashi Nakayama , Kumiaki Moriya , Masaki Matsumoto , Minoru Akita , Tsuyoshi Niino , Kanehiro Ochiai , Akihiko Shiozawa , Yuichi Uchiyama , Toyoharu Yasuno , Kenji Moriya , Shouichirou Kinoshita , Kazuo Kage , Ryuji Kubota
发明人： Kenji Tominaga , Minoru Miki , Tooru Takahashi , Tetsuo Horiuchi , Hideo Morishima , Takashi Nakayama , Kumiaki Moriya , Masaki Matsumoto , Minoru Akita , Tsuyoshi Niino , Kanehiro Ochiai , Akihiko Shiozawa , Yuichi Uchiyama , Toyoharu Yasuno , Kenji Moriya , Shouichirou Kinoshita , Kazuo Kage , Ryuji Kubota
摘要： A nuclear reactor facility including a primary containment vessel, a reactor pressure vessel installed in the primary containment vessel and accommodating a reactor core in a lower part thereof, and a vertical cylindrical wall disposed in a lower part of the primary containment vessel around and spaced from the reactor pressure vessel so as to delimit an annular space therebetween. The vertical cylindrical wall has an upper end disposed at a position higher than an upper end of the reactor core and a diaphragm extends substantially horizontally between the upper end of the vertical cylindrical wall and an inner wall of the primary containment vessel for cooperating with the vertical cylindrical wall to separate a space in the primary containment vessel around the reactor pressure vessel into a pressure suppression chamber and a drywell which includes annular space. The pressure suppression chamber accommodates therein a pool of liquid coolant wherein a level of the liquid coolant of the pool is higher than the upper end of the reactor core. The vertical cylindrical wall has a plurality of vent passages having an upper part at the upper end of the vertical cylindrical wall and exposed to the drywell and a lower part exposed to the pool of the liquid coolant in the pressure suppression chamber. A submergence line and a channel member are also provided.
摘要翻译： 一种核反应堆设备，其包括主要容纳容器，安装在初级容纳容器中的反应堆压力容器，并且在其下部容纳反应堆芯，以及设置在初级容纳容器的下部中的垂直圆柱形壁，并且间隔开 反应器压力容器，以便限定它们之间的环形空间。 垂直圆柱形壁的上端设置在高于反应堆芯的上端的位置，隔膜在垂直圆柱形壁的上端和主要容纳容器的内壁之间基本水平地延伸，用于与竖直的壁垂直 圆柱形壁将反应堆压力容器周围的初级容纳容器中的空间分离成压力抑制室和包括环形空间的干井。 压力抑制室容纳有液体冷却剂池，其中池的液体冷却剂的水平高于反应堆堆芯的上端。 垂直圆柱形壁具有多个排气通道，其具有在垂直圆柱形壁的上端处的上部并暴露于干井，下部暴露于压力抑制室中的液体冷却剂池中。 还提供淹没线和通道构件。
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公开(公告)号：US5011652A
公开(公告)日：1991-04-30
申请号：US98530
申请日：1987-09-18
申请人： Kenji Tominaga , Minoru Miki , Tooru Takahashi , Tetsuo Horiuchi , Hideo Morishima , Takashi Nakayama , Kumiaki Moriya , Masaki Matsumoto , Minoru Akita , Tsuyoshi Niino , Kanehiro Ochiai , Akihiko Shiozawa , Yuichi Uchiyama , Toyoharu Yasuno , Kenji Moriya , Shouichirou Kinoshita , Kazuo Kage , Ryuji Kubota
发明人： Kenji Tominaga , Minoru Miki , Tooru Takahashi , Tetsuo Horiuchi , Hideo Morishima , Takashi Nakayama , Kumiaki Moriya , Masaki Matsumoto , Minoru Akita , Tsuyoshi Niino , Kanehiro Ochiai , Akihiko Shiozawa , Yuichi Uchiyama , Toyoharu Yasuno , Kenji Moriya , Shouichirou Kinoshita , Kazuo Kage , Ryuji Kubota
IPC分类号： G21C15/18
摘要： A container-outer-periphery pool in which water is stored is provided between a primary containment vessel and a reactor building, and outside of a pressure suppression pool. Consequently, the natural heat transfer capabilities of reactor facilities is enhanced, and the inherent safety of the reactor facilities is improved.
摘要翻译： 在主要容纳容器和反应堆建筑物之间以及在压力抑制池外部提供储存有水的容器外周边池。 因此，反应堆设施的自然传热能力得到提高，反应堆设施的固有安全性得到提高。
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公开(公告)号：US4123327A
公开(公告)日：1978-10-31
申请号：US689817
申请日：1976-05-25
摘要： Fuel assemblies forming the core of a nuclear reactor each include an open-ended tubular channel, upper and lower tie plates formed therein with a multitude of through holes and arranged in the vicinity of upper and lower ends of the tubular channel respectively, and elongated fuel elements located parallel to one another and extending between the upper and lower tie plates. The channel of each fuel assembly is formed in its walls with openings which are disposed below the upper tie plate and above the upper end edge of the fuel of each fuel element.
摘要翻译： 形成核反应堆核心的燃料组件各自包括开口管状通道，其中形成有多个通孔并分别布置在管状通道的上端和下端附近的上下连接板和细长燃料 元件彼此平行并且在上和下连接板之间延伸。 每个燃料组件的通道在其壁中形成有开口，开口设置在上连接板的下方并且位于每个燃料元件的燃料的上端边缘之上。
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公开(公告)号：US20130224931A1
公开(公告)日：2013-08-29
申请号：US13884630
申请日：2012-03-21
申请人： Haruyuki Sorada , Takumi Mikawa , Kenji Tominaga , Kiyotaka Tsuji
发明人： Haruyuki Sorada , Takumi Mikawa , Kenji Tominaga , Kiyotaka Tsuji
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L27/101 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/04 , H01L45/1683
摘要： A method of manufacturing a nonvolatile memory device that is a variable resistance nonvolatile memory device, which has good consistency with a dual damascene process that is suitable for the formation of fine copper lines and which enables large capacity and high integration. This method includes: forming a variable resistance element, a contact hole and a line groove; and forming a current steering layer of a bidirectional diode element above interlayer insulating layers and a variable resistance layer to cover the line groove without covering a bottom surface of the contact hole.
摘要翻译： 一种制造非易失性存储器件的方法，其是可变电阻非易失性存储器件，其与适合于形成细铜线的双镶嵌工艺具有良好的一致性，并且能够实现大容量和高集成度。 该方法包括：形成可变电阻元件，接触孔和线槽; 并且在层间绝缘层之上形成双向二极管元件的电流转向层和可变电阻层以覆盖线槽而不覆盖接触孔的底表面。
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10.发明授权Current steering element, storage element, storage device, and method for manufacturing current steering element 有权目前的导向元件，存储元件，存储装置以及用于制造当前转向元件的方法公开(公告)号：US08355274B2
公开(公告)日：2013-01-15
申请号：US13061312
申请日：2009-09-17
申请人： Koji Arita , Takumi Mikawa , Mitsuteru IIjima , Kenji Tominaga
发明人： Koji Arita , Takumi Mikawa , Mitsuteru IIjima , Kenji Tominaga
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2013/0078 , G11C2213/15 , G11C2213/51 , G11C2213/56 , G11C2213/76 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A current steering element which can prevent occurrence of write disturb even when electric pulses having different polarities are applied and can cause large current to flow through a variable resistance element, and with which data can be written without problem. In a storage element (3) including: a variable resistance element (1) whose electric resistance value changes in response to application of electric pulses having a positive polarity and a negative polarity and which maintains the changed electric resistance value; and the current steering element (2) that steers current flowing through the variable resistance element (1) when the electric pulses are applied, the current steering element (2) includes: a first electrode (32); a second electrode (31); and a current steering layer (33) interposed between the first electrode (32) and the second electrode (31). When the current steering layer (33) includes SiNx (0
摘要翻译： 即使施加具有不同极性的电脉冲也能够防止写入干扰的发生，并且可能导致大的电流流过可变电阻元件并且可以无限制地写入数据的电流导向元件。 在一种存储元件（3）中，包括：可变电阻元件（1），其电阻值响应于具有正极性和负极性的电脉冲的应用而变化并且保持改变的电阻值; 以及当施加电脉冲时转向流过可变电阻元件（1）的电流的当前操舵元件（2），所述电流操舵元件（2）包括：第一电极（32）; 第二电极（31）; 和介于所述第一电极（32）和所述第二电极（31）之间的电流转向层（33）。 当电流导向层（33）包括SiNx（0
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