High input impedance, high gain CMOS strobed comparator
    1.
    发明授权
    High input impedance, high gain CMOS strobed comparator 失效
    高输入阻抗,高增益CMOS选通比较器

    公开(公告)号:US4717838A

    公开(公告)日:1988-01-05

    申请号:US931339

    申请日:1986-11-14

    CPC分类号: H03K3/35613

    摘要: A CMOS high gain strobed comparator comprising a cascoded input differential stage with current mirror loads. The DC biasing for the input stage cascode devices is set by a replica biasing technique. The loads to the input differential stage are simple current mirrors which drive a set of cross-coupled devices that form a latch. The high gain of the comparator is realized in the second stage. The differential output of the comparator drives a second latch. This second cross-coupled latch stores and maintains the comparator data even after the strobe signal destroys the data of the differential output.

    摘要翻译: CMOS高增益选通比较器,包括具有电流反射镜负载的级联输入差分级。 输入级共源共栅器件的直流偏置由复制偏置技术设置。 输入差分级的负载是简单的电流镜,其驱动形成锁存器的一组交叉耦合器件。 比较器的高增益在第二阶段实现。 比较器的差分输出驱动第二个锁存器。 即使在选通信号破坏差分输出的数据之后,该第二交叉耦合锁存器也存储和维持比较器数据。

    Method and apparatus for a CMOS image sensor with a distributed amplifier

    公开(公告)号:US6130423A

    公开(公告)日:2000-10-10

    申请号:US113395

    申请日:1998-07-10

    IPC分类号: H04N5/335 H01L27/00

    摘要: A CMOS image sensor circuit having a distributed amplifier is disclosed. The CMOS image sensor circuit is constructed using a photo sensor that converts light intensity to into voltage, a reset transistor to charge the photo sensor, and a distributed amplifier to detect and read out the voltage value created by the photo sensor. The distributed amplifier is distributed in the sense that portions of the amplifier circuitry reside within individual pixel circuits that form a CMOS image sensor array. The remainder of the amplifier resides in a column read out circuit that is at the bottom of the CMOS image sensor array.

    Large swing CMOS power amplifier
    4.
    发明授权
    Large swing CMOS power amplifier 失效
    大摆幅CMOS功率放大器

    公开(公告)号:US4480230A

    公开(公告)日:1984-10-30

    申请号:US510713

    申请日:1983-07-05

    摘要: A CMOS Class AB power amplifier is disclosed wherein supply-to-supply voltage swings across low resistive loads are efficiently and readily handled. A high gain input stage including a differential amplifier driving a common source amplifier drives unity gain push-pull output stage. Included in the invention is circuitry to control the DC bias current in the output driver devices in the event of an offset between the push-pull unity gain amplifiers.

    摘要翻译: 公开了一种CMOS AB类功率放大器,其中跨低电阻负载的电源电压摆幅被有效且容易地处理。 包括驱动公共源放大器的差分放大器的高增益输入级驱动单位增益推挽输出级。 本发明中包括在推挽单位增益放大器之间偏移的情况下控制输出驱动器件中的直流偏置电流的电路。

    Fabrication of semiconductor structure having two levels of buried
regions
    5.
    发明授权
    Fabrication of semiconductor structure having two levels of buried regions 失效
    具有两层埋藏区域的半导体结构的制造

    公开(公告)号:US5899714A

    公开(公告)日:1999-05-04

    申请号:US471061

    申请日:1995-06-06

    摘要: Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. An upper buried region of a selected conductivity type is situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. Another upper buried region of opposite conductivity type to the first-mentioned upper buried region is preferably situated along the upper semiconductor interface. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.

    摘要翻译: 适用于高性能应用的集成电路,特别是具有模拟和数字部分的混合信号产品由半导体结构制造,其中相反导电类型的较低掩埋区域沿着半导体衬底和上覆下层之间的下半导体界面 半导体层。 所选择的导电类型的上掩埋区域沿着下半导体层和上半导电层之间的上半导体界面设置。 优选地,与上述上部掩埋区域相反的导电类型的另一个上部掩埋区域沿着上半导体界面设置。 上半导体层包含晶体管区所在的P型和N型器件区。 半导体结构被配置为使得每个P型和N型器件区中的至少一个与衬底电隔离。 互补双极晶体管可以与结构中的互补场效应晶体管集成。

    Image sensor circuits including sampling circuits used therein for performing correlated double sampling
    7.
    发明授权
    Image sensor circuits including sampling circuits used therein for performing correlated double sampling 有权
    图像传感器电路包括用于执行相关双重采样的采样电路

    公开(公告)号:US07133074B1

    公开(公告)日:2006-11-07

    申请号:US09406979

    申请日:1999-09-28

    IPC分类号: H04N3/14 H04N5/335 H04N5/217

    CPC分类号: H04N5/335

    摘要: A CMOS image sensor circuit includes an array of sensing elements which integrate electrical charge according to the light intensity thereon. In order to measure the accumulated charge voltage at the individual sensing elements, and thus obtain the image data from the array, a sampling circuit is provided. The sampling circuit operates using a high-gain amplification stage and an auto-zero amplifier to perform correlated double sampling, which enables non-linear influences which may arise in the array to be reduced in the measuring process. The sampling circuit can also include a sample and hold circuit arranged to account for a feed-through effect arising from pre-charge circuitry in the sensing elements. The sample and hold circuit can be included within the feed-back loop of the high-gain amplification stage for further increases in linear performance.

    摘要翻译: CMOS图像传感器电路包括根据其上的光强度积分电荷的感测元件的阵列。 为了测量各个感测元件上的累积充电电压,从而从阵列获得图像数据,提供采样电路。 采样电路使用高增益放大级和自动调零放大器进行相关双采样,这使得能够在测量过程中减少阵列中可能出现的非线性影响。 采样电路还可以包括采样和保持电路,其布置成考虑由感测元件中的预充电电路产生的馈通效应。 采样和保持电路可以包括在高增益放大级的反馈回路中,用于线性性能的进一步增加。

    Method and architecture for an improved CMOS color image sensor
    8.
    发明授权
    Method and architecture for an improved CMOS color image sensor 有权
    改进的CMOS彩色图像传感器的方法和架构

    公开(公告)号:US07129978B1

    公开(公告)日:2006-10-31

    申请号:US09352494

    申请日:1999-07-13

    IPC分类号: H04N5/335

    摘要: According to the principles of this invention, an improved CMOS image sensor is disclosed. The improved CMOS image sensor comprises a pair of controllable column and row decoders, a signal conditioning circuit and a pixel processor in addition to an array of photo sensors. With the pair of controllable column and row decoders, photo sensors can selectively and dynamically accessed to improve signal throughput for applications that do not require the full set of signals from the array of photo sensors. The digitized signals from the selected photo sensors can be processed in the pixel processor for auto focus, pixel signals decimation and interpolation, data conversation and compression. Consequently, the design complexity of an overall imaging system using the disclosed CMOS image sensor is considerably reduced and the performance thereof is substantially increased.

    摘要翻译: 根据本发明的原理,公开了一种改进的CMOS图像传感器。 改进的CMOS图像传感器包括一对可控列和行解码器,信号调理电路和像素处理器以及光传感器阵列。 利用一对可控的列和行解码器,可以选择性地和动态地访问光传感器,以改善不需要来自光传感器阵列的全套信号的应用的信号吞吐量。 来自所选择的光传感器的数字化信号可以在像素处理器中进行处理,用于自动聚焦,像素信号抽取和插值,数据会话和压缩。 因此,使用所公开的CMOS图像传感器的整体成像系统的设计复杂性大大降低,并且其性能显着增加。

    Semiconductor structure having two levels of buried regions
    9.
    发明授权
    Semiconductor structure having two levels of buried regions 失效
    具有两层埋藏区域的半导体结构

    公开(公告)号:US5889315A

    公开(公告)日:1999-03-30

    申请号:US393622

    申请日:1995-02-23

    摘要: Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricatable from a semiconductor structure having two levels of buried regions. In a typical embodiment lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. Upper buried regions of opposite conductivity type are similarly situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is normally configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.

    摘要翻译: 适合于高性能应用的集成电路,特别是具有模拟和数字部分的混合信号产品,可从具有两级埋入区域的半导体结构制造。 在典型的实施例中,相反导电类型的较低掩埋区域沿着半导体衬底和上覆下半导体层之间的下半导体界面设置。 相反导电类型的上掩埋区类似地位于下半导体层和上半导电层之间的上半导体界面处。 上半导体层包含晶体管区所在的P型和N型器件区。 半导体结构通常被配置为使得每个P型和N型器件区域中的至少一个与衬底电隔离。 互补双极晶体管可以与结构中的互补场效应晶体管集成。

    Method and apparatus for a CMOS image sensor with a distributed amplifier
    10.
    发明授权
    Method and apparatus for a CMOS image sensor with a distributed amplifier 有权
    具有分布式放大器的CMOS图像传感器的方法和装置

    公开(公告)号:US07157682B2

    公开(公告)日:2007-01-02

    申请号:US09957343

    申请日:2001-09-19

    IPC分类号: H01L27/00 H04N5/335

    CPC分类号: H04N5/378 H04N5/374 H04N5/376

    摘要: A CMOS image sensor circuit having a distributed amplifier is disclosed. The CMOS image sensor circuit is constructed using a photo sensor that converts light intensity to into voltage, a reset transistor to charge the photo sensor, and a distributed amplifier to detect and read out the voltage value created by the photo sensor. The distributed amplifier is distributed in the sense that portions of the amplifier circuitry reside within individual pixel circuits that form a CMOS image sensor array. The remainder of the amplifier resides in a column read out circuit that is at the bottom of the CMOS image sensor array.

    摘要翻译: 公开了具有分布式放大器的CMOS图像传感器电路。 CMOS图像传感器电路使用将光强度转换为电压的光电传感器构成,复位晶体管对光电传感器充电,以及分布式放大器来检测和读出由光电传感器产生的电压值。 分布式放大器的分布是指放大器电路的部分驻留在形成CMOS图像传感器阵列的各个像素电路内。 放大器的其余部分位于CMOS图像传感器阵列底部的列读出电路中。