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23 条记录 (耗时 0.016 秒)

    INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF
    1.
    发明申请
    INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF 有权
    具有分层电容器的集成电路系统及其制造方法

    公开(公告)号：US20120007214A1

    公开(公告)日：2012-01-12

    申请号：US13236295

    申请日：2011-09-19

    申请人： Shao-fu Sanford Chu ,  Shaoqiang Zhang ,  Johnny Kok Wai Chew

    发明人： Shao-fu Sanford Chu ,  Shaoqiang Zhang ,  Johnny Kok Wai Chew

    IPC分类号： H01L29/92 ,  H01L21/20

    CPC分类号： H01L23/5223 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor.

    摘要翻译： 一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且互连所述第一组金属层，包括互连与第二簇相邻的第一簇，以形成电容器。

    Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology
    2.
    发明授权
    Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology 有权
    在硅基板上捕获空气的方法，以改善CMOS技术中RF电感器的品质因素

    公开(公告)号：US06221727B1

    公开(公告)日：2001-04-24

    申请号：US09385524

    申请日：1999-08-30

    申请人： Lap Chan ,  Johnny Kok Wai Chew ,  Cher Liang Cha ,  Chee Tee Chua

    发明人： Lap Chan ,  Johnny Kok Wai Chew ,  Cher Liang Cha ,  Chee Tee Chua

    IPC分类号： H01L2120

    CPC分类号： H01L28/10 ,  H01L21/764 ,  H01L27/08

    摘要： A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacturing of integrated circuits is described. A field oxide region is formed in and on a semiconductor substrate and then removed whereby a well is left in the semiconductor substrate. A polish stop layer is deposited over the substrate and within the well. The polish stop layer is covered and the well filled with a spin-on-glass layer. The spin-on-glass layer is polished back to the polish stop layer. The said polish stop layer is removed. A first oxide layer is deposited overlying the spin-on-glass layer and the semiconductor substrate and is patterned using an inductor reticle whereby a plurality of openings are made through the first oxide layer to the spin-on-glass layer. All of the spin-on-glass layer within the well is removed through the plurality of openings. Thereafter, a second oxide layer is deposited overlying the first oxide layer and capping the plurality of openings thereby forming an air barrier within the well. A metal layer is deposited overlying the second oxide layer and patterned using the same inductor reticle to form the inductor in the fabrication of an integrated circuit device.

    摘要翻译： 描述了在制造集成电路中制造利用空气作为下层屏障的电感器的新方法。 在半导体衬底中形成场氧化物区域，然后去除，从而在半导体衬底中留下阱。 抛光停止层沉积在基底上并在孔内。 抛光停止层被覆盖并充满了旋涂玻璃层。 旋涂玻璃层被抛光回抛光停止层。 所述抛光停止层被去除。 沉积在旋涂玻璃层和半导体衬底上的第一氧化物层，并且使用电感器掩模版进行图案化，由此通过第一氧化物层到旋涂玻璃层制成多个开口。 孔内的所有旋涂玻璃层通过多个开口被去除。 此后，将第二氧化物层沉积在第一氧化物层上并覆盖多个开口，从而在该阱内形成空气屏障。 沉积在第二氧化物层上的金属层，并使用相同的电感器掩模版进行图案化以在集成电路器件的制造中形成电感器。

    Integrated circuit system with hierarchical capacitor and method of manufacture thereof
    3.
    发明授权
    Integrated circuit system with hierarchical capacitor and method of manufacture thereof 有权
    具有分层电容器的集成电路系统及其制造方法

    公开(公告)号：US08536016B2

    公开(公告)日：2013-09-17

    申请号：US13236295

    申请日：2011-09-19

    申请人： Shao-fu Sanford Chu ,  Shaoqiang Zhang ,  Johnny Kok Wai Chew

    发明人： Shao-fu Sanford Chu ,  Shaoqiang Zhang ,  Johnny Kok Wai Chew

    IPC分类号： H01L21/20

    CPC分类号： H01L23/5223 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor.

    摘要翻译： 一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且互连所述第一组金属层，包括互连与第二簇相邻的第一簇，以形成电容器。

    Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology
    5.
    发明授权
    Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology 有权
    用于铜后端（BEOL）技术的金属绝缘体金属（MIM）电容器和金属电阻器的制造方法

    公开(公告)号：US06709918B1

    公开(公告)日：2004-03-23

    申请号：US10307674

    申请日：2002-12-02

    申请人： Chit Hwei Ng ,  Jian Xun Li ,  Kok Wai Chew ,  Tjin Tjin Tjoa ,  Chaw Sing Ho ,  Shao Fu Sanford Chu

    发明人： Chit Hwei Ng ,  Jian Xun Li ,  Kok Wai Chew ,  Tjin Tjin Tjoa ,  Chaw Sing Ho ,  Shao Fu Sanford Chu

    IPC分类号： H01L218242

    CPC分类号： H01L28/20 ,  H01L23/5223 ,  H01L23/5228 ,  H01L28/40 ,  H01L2924/0002 ,  Y10S438/959 ,  H01L2924/00

    摘要： A method for making concurrently metal-insulator-metal (MIM) capacitors and a metal resistors in a Cu damascene back-end-of-line process is achieved. The method forms a Cu capacitor bottom metal plate using a dual-damascene process. A Si3N4 or SiC is deposited to form a capacitor dielectric layer on the Cu bottom plate. A metal layer having an upper etch-stop layer is deposited and patterned to form concurrently capacitor top plates and metal resistors. The patterning is terminated in the capacitor dielectric layer to prevent Cu particle contamination. An insulating layer is deposited and via holes are etched to the capacitor top plates and the metal resistors using the upper etch-stop layer to prevent overetching and damage. The method provides a MIM capacitor using only one additional photoresist mask while improving process yield.

    摘要翻译： 实现了一种在金铜绝缘体金属（MIM）电容器和金属电阻器Cu铜镶嵌后端工艺中的制造方法。 该方法使用双镶嵌工艺形成Cu电容器底部金属板。 沉积Si 3 N 4或SiC以在Cu底板上形成电容器电介质层。 具有上蚀刻停止层的金属层被沉积​​并图案化以形成电容器顶板和金属电阻器。 图案化终止在电容器电介质层中以防止Cu颗粒污染。 沉积绝缘层，并且使用上蚀刻停止层将电容器顶板和金属电阻器的通孔蚀刻以防止过蚀刻和损坏。 该方法提供了仅使用一种附加光致抗蚀剂掩模的MIM电容器，同时提高了工艺产量。

    Technique to generate negative conductance in CMOS tuned cascode RF amplifiers
    8.
    发明授权
    Technique to generate negative conductance in CMOS tuned cascode RF amplifiers 失效
    在CMOS调谐共源共RF放大器中产生负电导的技术

    公开(公告)号：US06292060B1

    公开(公告)日：2001-09-18

    申请号：US09395288

    申请日：1999-09-13

    申请人： Kiat-Seng Yeo ,  Kok Lim Chan ,  Manh Anh Do ,  Jian Guo Ma ,  Johnny Kok Wai Chew

    发明人： Kiat-Seng Yeo ,  Kok Lim Chan ,  Manh Anh Do ,  Jian Guo Ma ,  Johnny Kok Wai Chew

    IPC分类号： H03F3191

    CPC分类号： H03F1/56 ,  H03F1/223 ,  H03F2200/294 ,  H03F2200/369 ,  H03F2200/372

    摘要： In this invention a single additional capacitor is added to a tuned cascode LNA which boosts the circuit Q and the gain of the amplifier. The added capacitor creates a negative real part of the impedance which when combined with the impedance of the LC tank circuit improves both the Q and the gain of the amplifier. The capacitor does not dissipate any power, and being a passive device the capacitor does not add additional noise to the circuit. With an improved gain there is a much improved signal to noise ratio. The higher Q allows the amplifier to provide some additional bandpass and reduce image reduction requirements in subsequent amplifier stages.

    摘要翻译： 在本发明中，将单个附加电容器添加到调谐共源共栅LNA，其升高电路Q和放大器的增益。 增加的电容产生阻抗的负实部，当与LC谐振电路的阻抗相结合时，可以提高放大器的Q和增益。 电容器不会耗散任何电源，而作为无源器件，电容器不会对电路增加额外的噪声。 随着改进的增益，信噪比有了很大改善。 较高的Q允许放大器提供一些额外的带通，并降低后续放大器级中的图像降低要求。

    Integrated transformer
    9.
    发明授权
    Integrated transformer 有权
    集成变压器

    公开(公告)号：US08643461B2

    公开(公告)日：2014-02-04

    申请号：US13095932

    申请日：2011-04-28

    申请人： Chee Chong Lim ,  Johnny Kok Wai Chew ,  Suh Fei Lim ,  Wei Gao

    发明人： Chee Chong Lim ,  Johnny Kok Wai Chew ,  Suh Fei Lim ,  Wei Gao

    IPC分类号： H01F5/00

    CPC分类号： H01L23/5227 ,  H01F19/04 ,  H01F2027/2809 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device having a substrate and a dielectric layer disposed over the substrate is disclosed. The device includes a transformer layout disposed in the dielectric layer. The transformer layout includes an integrated transformer having primary and secondary coil elements. The first and second coil elements are configured to result in noise-self cancellation effect.

    摘要翻译： 公开了一种具有衬底和设置在衬底上的电介质层的器件。 该装置包括布置在电介质层中的变压器布局。 变压器布局包括具有初级和次级线圈元件的集成变压器。 第一和第二线圈元件被配置成导致噪声自消除效应。

    INTEGRATED TRANSFORMER
    10.
    发明申请
    INTEGRATED TRANSFORMER 有权
    集成变压器

    公开(公告)号：US20120274434A1

    公开(公告)日：2012-11-01

    申请号：US13095932

    申请日：2011-04-28

    申请人： Chee Chong LIM ,  Johnny Kok Wai CHEW ,  Suh Fei LIM ,  Wei GAO

    发明人： Chee Chong LIM ,  Johnny Kok Wai CHEW ,  Suh Fei LIM ,  Wei GAO

    IPC分类号： H01F5/00 ,  H01F41/04

    CPC分类号： H01L23/5227 ,  H01F19/04 ,  H01F2027/2809 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device having a substrate and a dielectric layer disposed over the substrate is disclosed. The device includes a transformer layout disposed in the dielectric layer. The transformer layout includes an integrated transformer having primary and secondary coil elements. The first and second coil elements are configured to result in noise-self cancellation effect.

    摘要翻译： 公开了一种具有衬底和设置在衬底上的电介质层的器件。 该装置包括布置在电介质层中的变压器布局。 变压器布局包括具有初级和次级线圈元件的集成变压器。 第一和第二线圈元件被配置成导致噪声自消除效应。