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公开(公告)号：US08664929B2
公开(公告)日：2014-03-04
申请号：US13307644
申请日：2011-11-30
Applicant: Po-Chin Fan , Kuo-Ping Liu
Inventor： Po-Chin Fan , Kuo-Ping Liu
IPC: G05F1/00
CPC classification number: H02M3/1588 , H02M2001/0025 , H02M2001/0032 , Y02B70/1466 , Y02B70/16
Abstract: When the switching frequency of a constant on-time power converter decreases to a threshold, the power converter is switched from the original operation of triggering a constant on-time of a high-side switch responsive to the output voltage of the power converter reaching a valley point to the operation of triggering a constant off-time of the high-side switch responsive to the output voltage reaching a peak point, to thereby prevent the power converter from operating in an audio frequency range.
Abstract translation: 当恒定导通时间功率转换器的开关频率降低到阈值时，响应于功率转换器的输出电压到达高功率转换器的输出电压，功率转换器从原始操作切换到触发高侧开关的恒定导通时间 谷指向响应于输出电压达到峰值点的高侧开关的恒定关断时间的操作，从而防止功率转换器在音频范围内工作。
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2.发明授权公开(公告)号：US07834606B2
公开(公告)日：2010-11-16
申请号：US11882485
申请日：2007-08-02
Applicant: Kuo-Ping Liu , Ko-Cheng Wang , Liang-Pin Tai , Chung-Sheng Cheng
Inventor： Kuo-Ping Liu , Ko-Cheng Wang , Liang-Pin Tai , Chung-Sheng Cheng
IPC: G05F1/00
CPC classification number: H02M3/157 , H02M2001/0048 , Y02B70/1491
Abstract: A control circuit provides a control signal for a constant on-time PWM switching converter to produce an output voltage, such that the converter operates with a constant on-time at a first state and operates with a variable on-time at a second state, so as to decrease the switching frequency and thereby the switching loss, to increase the efficiency of the converter, to improve the transient response, and to reduce the recovery time of the output voltage.
Abstract translation: 控制电路提供用于恒定导通时间PWM开关转换器的控制信号以产生输出电压，使得转换器在第一状态下以恒定导通时间工作，并且在第二状态下以可变导通时间操作， 从而降低开关频率，从而降低开关损耗，提高转换器的效率，改善瞬态响应，并减少输出电压的恢复时间。
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3.发明申请公开(公告)号：US20100283441A1
公开(公告)日：2010-11-11
申请号：US12766246
申请日：2010-04-23
Applicant: Ko-Cheng Wang , Kuo-Ping Liu , Chih-Wei Tseng
Inventor： Ko-Cheng Wang , Kuo-Ping Liu , Chih-Wei Tseng
IPC: G05F1/10
CPC classification number: H02M3/1588 , H02M1/14 , Y02B70/1466
Abstract: A PWM controller and control method for a DC-DC voltage converter filter the high-frequency component of the voltage at the phase node between high-side and low-side elements of the voltage converter to generate a signal synchronous and in phase or out-of-phase with the inductor current of the voltage converter, to achieve a low-ripple output voltage and stable loop control.
Abstract translation: 用于DC-DC电压转换器的PWM控制器和控制方法对电压转换器的高侧和低侧元件之间的相位节点处的电压的高频分量进行滤波，以产生同步和相位或相位的信号， 与电压转换器的电感电流相位，实现低纹波输出电压和稳定的环路控制。
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4.发明申请公开(公告)号：US20080030181A1
公开(公告)日：2008-02-07
申请号：US11882485
申请日：2007-08-02
Applicant: Kuo Ping Liu , Ko Cheng Wang , Liang Pin Tai , Chung Sheng Cheng
Inventor： Kuo Ping Liu , Ko Cheng Wang , Liang Pin Tai , Chung Sheng Cheng
CPC classification number: H02M3/157 , H02M2001/0048 , Y02B70/1491
Abstract: A control circuit provides a control signal for a constant on-time PWM switching converter to produce an output voltage, such that the converter operates with a constant on-time at a first state and operates with a variable on-time at a second state, so as to decrease the switching frequency and thereby the switching loss, to increase the efficiency of the converter, to improve the transient response, and to reduce the recovery time of the output voltage.
Abstract translation: 控制电路提供用于恒定导通时间PWM开关转换器的控制信号以产生输出电压，使得转换器在第一状态下以恒定导通时间工作，并且在第二状态下以可变导通时间操作， 从而降低开关频率，从而降低开关损耗，提高转换器的效率，改善瞬态响应，并减少输出电压的恢复时间。
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公开(公告)号：US06969980B1
公开(公告)日：2005-11-29
申请号：US10850164
申请日：2004-05-21
Applicant: Liang-Pin Tai , Kent Hwang , Jian-Rong Huang , Kuo-Ping Liu , Cheng-Hsuan Fan , Ko-Cheng Wang , Yu-Fan Liao
Inventor： Liang-Pin Tai , Kent Hwang , Jian-Rong Huang , Kuo-Ping Liu , Cheng-Hsuan Fan , Ko-Cheng Wang , Yu-Fan Liao
CPC classification number: H02M1/08
Abstract: A pulse width modulator includes an amplifier module, a comparator module, and a filter module. The amplifier module receives a feedback voltage signal from a passive network, and generates first and second non-inverted voltage signals and first and second inverted voltage signals in response to the feedback voltage signal. The comparator module receives the first and second non-inverted voltage signals and the first and second inverted voltage signals, and provides first and second differential voltage signals corresponding to the first and second non-inverted voltage signals and the first and second inverted voltage signals. The filter module is coupled between the amplifier module and the comparator module, and is operable so as to attenuate high frequency components of the first and second non-inverted voltage signals. As such, the presence of noise in the feedback voltage signal does not affect differential operation of the comparator module.
Abstract translation: 脉冲宽度调制器包括放大器模块，比较器模块和滤波器模块。 放大器模块从无源网络接收反馈电压信号，并响应于反馈电压信号产生第一和第二非反相电压信号以及第一和第二反相电压信号。 比较器模块接收第一和第二非反相电压信号以及第一和第二反相电压信号，并提供对应于第一和第二非反相电压信号以及第一和第二反相电压信号的第一和第二差分电压信号。 滤波器模块耦合在放大器模块和比较器模块之间，并且可操作以便衰减第一和第二非反相电压信号的高频分量。 因此，反馈电压信号中的噪声的存在不会影响比较器模块的差分工作。
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Patent Agency Ranking
6.发明申请Apparatus and method for noise sensitivity improvement to a switching system 失效对开关系统进行噪声敏感度改进的装置和方法公开(公告)号：US20050017767A1
公开(公告)日：2005-01-27
申请号：US10882159
申请日：2004-07-02
Applicant: Jian-Rong Huang , Kuo-Ping Liu , Kent Huang , Liang-Pin Tai
Inventor： Jian-Rong Huang , Kuo-Ping Liu , Kent Huang , Liang-Pin Tai
CPC classification number: H03F3/217 , H02M3/1588 , H03K7/08 , Y02B70/1466
Abstract: In a noise sensitivity improved switching system and method thereof, comprised sensing the output voltage of the switching system to generate a feedback signal, respectively amplifying the feedback signal by two gains to generate two signals in phase or out of phase, filtering one of the two amplified signals, and summing or comparing the filtered signal and the other one, thereby reducing the noise interference to the switching system.
Abstract translation: 在噪声敏感度改进的开关系统及其方法中，包括感测开关系统的输出电压以产生反馈信号，分别通过两个增益来放大反馈信号以产生相或异相的两个信号，滤波两个 放大信号，并对滤波后的信号进行求和或比较，从而降低对交换系统的噪声干扰。
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7.发明授权Computer chip set for computer mother board referencing various clock rates 失效计算机芯片组用于计算机主板，参考各种时钟频率公开(公告)号：US06202167B1
公开(公告)日：2001-03-13
申请号：US09099977
申请日：1998-06-19
Applicant: Jiin Lai , Heng-Chen Ho , Kuo-Ping Liu
Inventor： Jiin Lai , Heng-Chen Ho , Kuo-Ping Liu
IPC: G06F108
CPC classification number: G06F1/08
Abstract: A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other clock rate. The first and second clock rates are in virtual synchronism and have a fixed ratio between them. The computer chip set utilizes a phase signal generator capable of generating a set of phase signals and a signal conversion logic circuit for generating the output signal referencing one of the first and second clock rates other than the one referenced by the input signal. This computer chip set can allow the computer mother board to be operated without waiting a state so that the data processing efficiency of the computer mother board can be enhanced. A multiplexer means used in the computer chip set of the invention has an output which is selectively multiplexed between the first clock rate and the second clock rate to serve as a third clock signal. This computer chip set allows the designer to use a slower clock rate to drive the DRAM.
Abstract translation: 计算机芯片组被设计为在具有至少两个时钟速率的计算机母板上使用，包括第一时钟速率和第二时钟速率，用于将参考第一或第二时钟速率的输入信号转换为参考的输出信号 另一个时钟速率。 第一和第二时钟速率是虚拟同步的，并且它们之间具有固定的比例。 计算机芯片组利用能够产生一组相位信号的相位信号发生器和信号转换逻辑电路，用于产生参考第一和第二时钟速率之一的输出信号，而不是由输入信号所参考的那个。 该计算机芯片组可以允许计算机母板在不等待状态的情况下操作，从而可以提高计算机母板的数据处理效率。 在本发明的计算机芯片组中使用的多路复用器装置具有在第一时钟速率和第二时钟速率之间选择性地多路复用以用作第三时钟信号的输出。 该计算机芯片组允许设计者使用较慢的时钟速率来驱动DRAM。
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8.发明授权Computer chip set for computer mother board referencing various clock rates 失效计算机芯片组用于计算机主板，参考各种时钟频率
公开(公告)号：US06079027A
公开(公告)日：2000-06-20
申请号：US100515
申请日：1998-06-19
Applicant: Jiin Lai , Heng-Chen Ho , Kuo-Ping Liu
Inventor： Jiin Lai , Heng-Chen Ho , Kuo-Ping Liu
CPC classification number: G06F1/08
Abstract: A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other clock rate. The first and second clock rates are in virtual synchronism and have a fixed ratio between them. The computer chip set utilizes a phase signal generator capable of generating a set of phase signals and a signal conversion logic circuit for generating the output signal referencing one of the first and second clock rates other than the one referenced by the input signal. This computer chip set can allow the computer mother board to be operated without waiting a state so that the data processing efficiency of the computer mother board can be enhanced. A multiplexer means used in the computer chip set of the invention has an output which is selectively muliplexed between the first clock rate and the second clock rate to serve as a third clock signal. This computer chip set allows the designer to use a slower clock rate to drive the DRAM.
Abstract translation: 计算机芯片组被设计为在具有至少两个时钟速率的计算机母板上使用，包括第一时钟速率和第二时钟速率，用于将参考第一或第二时钟速率的输入信号转换为参考的输出信号 另一个时钟速率。 第一和第二时钟速率是虚拟同步的，并且它们之间具有固定的比例。 计算机芯片组利用能够产生一组相位信号的相位信号发生器和信号转换逻辑电路，用于产生参考第一和第二时钟速率之一的输出信号，而不是由输入信号所参考的那个。 该计算机芯片组可以允许计算机母板在不等待状态的情况下操作，从而可以提高计算机母板的数据处理效率。 在本发明的计算机芯片组中使用的多路复用器装置具有在第一时钟速率和第二时钟速率之间选择性地混合以用作第三时钟信号的输出。 该计算机芯片组允许设计者使用较慢的时钟速率来驱动DRAM。
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公开(公告)号：US20050258813A1
公开(公告)日：2005-11-24
申请号：US10850164
申请日：2004-05-21
Applicant: Liang-Pin Tai , Kent Hwang , Jian-Rong Huang , Kuo-Ping Liu , Cheng-Hsuan Fan , Ko-Cheng Wang , Yu-Fan Liao
Inventor： Liang-Pin Tai , Kent Hwang , Jian-Rong Huang , Kuo-Ping Liu , Cheng-Hsuan Fan , Ko-Cheng Wang , Yu-Fan Liao
CPC classification number: H02M1/08
Abstract: A pulse width modulator includes an amplifier module, a comparator module, and a filter module. The amplifier module receives a feedback voltage signal from a passive network, and generates first and second non-inverted voltage signals and first and second inverted voltage signals in response to the feedback voltage signal. The comparator module receives the first and second non-inverted voltage signals and the first and second inverted voltage signals, and provides first and second differential voltage signals corresponding to the first and second non-inverted voltage signals and the first and second inverted voltage signals. The filter module is coupled between the amplifier module and the comparator module, and is operable so as to attenuate high frequency components of the first and second non-inverted voltage signals. As such, the presence of noise in the feedback voltage signal does not affect differential operation of the comparator module.
Abstract translation: 脉冲宽度调制器包括放大器模块，比较器模块和滤波器模块。 放大器模块从无源网络接收反馈电压信号，并响应于反馈电压信号产生第一和第二非反相电压信号以及第一和第二反相电压信号。 比较器模块接收第一和第二非反相电压信号以及第一和第二反相电压信号，并提供对应于第一和第二非反相电压信号以及第一和第二反相电压信号的第一和第二差分电压信号。 滤波器模块耦合在放大器模块和比较器模块之间，并且可操作以便衰减第一和第二非反相电压信号的高频分量。 因此，反馈电压信号中的噪声的存在不会影响比较器模块的差分工作。
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公开(公告)号：US20120133348A1
公开(公告)日：2012-05-31
申请号：US13307644
申请日：2011-11-30
Applicant: Po-Chin FAN , Kuo-Ping LIU
Inventor： Po-Chin FAN , Kuo-Ping LIU
IPC: G05F1/10
CPC classification number: H02M3/1588 , H02M2001/0025 , H02M2001/0032 , Y02B70/1466 , Y02B70/16
Abstract: When the switching frequency of a constant on-time power converter decreases to a threshold, the power converter is switched from the original operation of triggering a constant on-time of a high-side switch responsive to the output voltage of the power converter reaching a valley point to the operation of triggering a constant off-time of the high-side switch responsive to the output voltage reaching a peak point, to thereby prevent the power converter from operating in an audio frequency range.
Abstract translation: 当恒定导通时间功率转换器的开关频率降低到阈值时，响应于功率转换器的输出电压到达高功率转换器的输出电压，功率转换器从原始操作切换到触发高侧开关的恒定导通时间 谷指向响应于输出电压达到峰值点的高侧开关的恒定关断时间的操作，从而防止功率转换器在音频范围内工作。
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