公开(公告)号：US20090020847A1

公开(公告)日：2009-01-22

申请号：US12216820

申请日：2008-07-11

Applicant: Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

Inventor： Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

IPC: H01L21/762 ,  H01L23/58

CPC classification number: H01L21/76229

Abstract: A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height. First and second upper material layer patterns may be formed on the first and second lower material layer patterns, respectively.

Abstract translation: 提供了具有沟槽隔离区域的半导体器件及其制造方法。 该方法包括在衬底中形成第一沟槽区域和在衬底中具有比第一沟槽区域宽的宽度的第二沟槽区域。 下部材料层可以填充第一和第二沟槽区域。 可以通过第一蚀刻工艺蚀刻下部材料层，以形成残留在第一沟槽区域中的第一初步下部材料层图案，并形成保留在第二沟槽区域中的第二预备下部材料层图案。 第二初步下层材料层图案的上表面可以处于与第一预备下层材料层图案不同的高度。 可以通过第二蚀刻工艺蚀刻第一和第二初级下部材料层图案，以形成具有基本上相同高度的顶表面的第一和第二下部材料层图案。 可以分别在第一和第二下部材料层图案上形成第一和第二上部材料层图案。

公开(公告)号：US08624354B2

公开(公告)日：2014-01-07

申请号：US12829864

申请日：2010-07-02

Applicant: Shin-hye Kim ,  Kyung-mun Byun ,  Hong-rae Kim ,  Gil-heyun Choi ,  Eun-kee Hong

Inventor： Shin-hye Kim ,  Kyung-mun Byun ,  Hong-rae Kim ,  Gil-heyun Choi ,  Eun-kee Hong

IPC: H01L21/02

CPC classification number: H01L27/10817 ,  H01L27/10852 ,  H01L28/91

Abstract: A semiconductor device may include a semiconductor substrate and a plurality of three-dimensional capacitors on the semiconductor substrate. Each of the plurality of three-dimensional capacitors may include a first three-dimensional electrode, a capacitor dielectric layer, and a second three-dimensional electrode with the first three-dimensional electrode between the capacitor dielectric layer and the semiconductor substrate and with the capacitor dielectric layer between the first and second three-dimensional electrodes. A plurality of capacitor support pads may be provided with each capacitor support pad being arranged between adjacent first three-dimensional electrodes of adjacent three-dimensional capacitors with portions of the capacitor dielectric layers between the capacitor support pads and the semiconductor substrate. Related methods and apparatuses are also discussed.

Abstract translation: 半导体器件可以包括半导体衬底和半导体衬底上的多个三维电容器。 多个三维电容器中的每一个可以包括第一三维电极，电容器电介质层和第二三维电极，其中在电容器介电层和半导体衬底之间具有第一三维电极，并且与电容器 第一和第二三维电极之间的介电层。 可以设置多个电容器支撑焊盘，每个电容器支撑焊盘布置在相邻的三维电容器的相邻的第一三维电极之间，其中电容器电介质层的一部分在电容器支撑焊盘和半导体衬底之间。 还讨论了相关的方法和装置。

公开(公告)号：US07781304B2

公开(公告)日：2010-08-24

申请号：US12216820

申请日：2008-07-11

Applicant: Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

Inventor： Kyung-Mun Byun ,  Ju-Seon Goo ,  Sang-Ho Rha ,  Eun-Kyung Baek ,  Jong-Wan Choi

IPC: H01L21/76

CPC classification number: H01L21/76229

Abstract: A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height. First and second upper material layer patterns may be formed on the first and second lower material layer patterns, respectively.

Abstract translation: 提供了具有沟槽隔离区域的半导体器件及其制造方法。 该方法包括在衬底中形成第一沟槽区域和在衬底中具有比第一沟槽区域宽的宽度的第二沟槽区域。 下部材料层可以填充第一和第二沟槽区域。 可以通过第一蚀刻工艺蚀刻下部材料层，以形成残留在第一沟槽区域中的第一初步下部材料层图案，并形成保留在第二沟槽区域中的第二预备下部材料层图案。 第二初步下层材料层图案的上表面可以处于与第一预备下层材料层图案不同的高度。 可以通过第二蚀刻工艺蚀刻第一和第二初级下部材料层图案，以形成具有基本上相同高度的顶表面的第一和第二下部材料层图案。 可以分别在第一和第二下部材料层图案上形成第一和第二上部材料层图案。

公开(公告)号：US20090045483A1

公开(公告)日：2009-02-19

申请号：US12222630

申请日：2008-08-13

Applicant: Sang-Ho Rha ,  Eun-Kee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek

Inventor： Sang-Ho Rha ,  Eun-Kee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek

IPC: H01L21/762 ,  H01L23/58

CPC classification number: H01L21/76232

Abstract: A semiconductor device may include a semiconductor substrate, trench region, buffer pattern, gap fill layer, and transistor. The trench region may be provided in the semiconductor substrate to define an active region. The buffer pattern and gap fill layer may be provided in the trench region. The buffer pattern and gap fill layer may fill the trench region. The gap fill layer may be densified by the buffer pattern. The transistor may be provided in the active region. A method of manufacturing a semiconductor device may include: forming a trench region in a semiconductor substrate; forming a buffer layer on an inner wall of the first trench region; forming a gap fill layer, filling the trench region; performing a thermal process to react the impurity with the oxygen, forming a buffer pattern; and forming a transistor in the active region.

Abstract translation: 半导体器件可以包括半导体衬底，沟槽区，缓冲图案，间隙填充层和晶体管。 沟槽区域可以设置在半导体衬底中以限定有源区域。 缓冲图案和间隙填充层可以设置在沟槽区域中。 缓冲图案和间隙填充层可以填充沟槽区域。 间隙填充层可以由缓冲图案致密化。 晶体管可以设置在有源区中。 半导体器件的制造方法可以包括：在半导体衬底中形成沟槽区域; 在所述第一沟槽区的内壁上形成缓冲层; 形成间隙填充层，填充沟槽区域; 进行热处理以使杂质与氧反应，形成缓冲图案; 以及在有源区中形成晶体管。

公开(公告)号：US20110115051A1

公开(公告)日：2011-05-19

申请号：US12829864

申请日：2010-07-02

Applicant: Shin-hye Kim ,  Kyung-mun Byun ,  Hong-rae Kim ,  Gil-heyun Choi ,  Eun-kee Hong

Inventor： Shin-hye Kim ,  Kyung-mun Byun ,  Hong-rae Kim ,  Gil-heyun Choi ,  Eun-kee Hong

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L27/10817 ,  H01L27/10852 ,  H01L28/91

Abstract: A semiconductor device may include a semiconductor substrate and a plurality of three-dimensional capacitors on the semiconductor substrate. Each of the plurality of three-dimensional capacitors may include a first three-dimensional electrode, a capacitor dielectric layer, and a second three-dimensional electrode with the first three-dimensional electrode between the capacitor dielectric layer and the semiconductor substrate and with the capacitor dielectric layer between the first and second three-dimensional electrodes. A plurality of capacitor support pads may be provided with each capacitor support pad being arranged between adjacent first three-dimensional electrodes of adjacent three-dimensional capacitors with portions of the capacitor dielectric layers between the capacitor support pads and the semiconductor substrate. Related methods and apparatuses are also discussed.

Abstract translation: 半导体器件可以包括半导体衬底和半导体衬底上的多个三维电容器。 多个三维电容器中的每一个可以包括第一三维电极，电容器电介质层和第二三维电极，其中在电容器介电层和半导体衬底之间具有第一三维电极，并且与电容器 第一和第二三维电极之间的介电层。 可以设置多个电容器支撑焊盘，每个电容器支撑焊盘布置在相邻的三维电容器的相邻的第一三维电极之间，其中电容器电介质层的一部分在电容器支撑焊盘和半导体衬底之间。 还讨论了相关的方法和装置。

公开(公告)号：US07858492B2

公开(公告)日：2010-12-28

申请号：US12339125

申请日：2008-12-19

Applicant: Eunkee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek ,  Young-Sun Kim

Inventor： Eunkee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek ,  Young-Sun Kim

IPC: H01L21/76

CPC classification number: H01L21/76237 ,  H01L21/76232

Abstract: A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material.

Abstract translation: 在衬底中填充沟槽的方法确保在占据沟槽的材料中不留下空隙或接缝。 首先，形成预备绝缘层，以沿着沟槽的底部和侧面并且沿衬底的上表面连续延伸。 然后将杂质注入到与第一沟槽的顶部相邻的初级绝缘层的一部分中，以形成具有掺杂区域和未掺杂区域的第一绝缘层。 去除掺杂区域以在第一沟槽的底部和侧面形成第一绝缘层图案，并且该第一绝缘层图案限定第二沟槽。 然后用绝缘材料填充第二沟槽。

公开(公告)号：US20100240194A1

公开(公告)日：2010-09-23

申请号：US12659841

申请日：2010-03-23

Applicant: DeokYoung Jung ,  Ju-Seon Goo ,  Kyung-Mun Byun ,  Eunkee Hong ,  Jun-Won Lee

Inventor： DeokYoung Jung ,  Ju-Seon Goo ,  Kyung-Mun Byun ,  Eunkee Hong ,  Jun-Won Lee

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76232

Abstract: A method of fabricating a semiconductor device, the method including sequentially forming a pad oxide layer and a nitride layer on a substrate; etching the nitride layer, the pad oxide layer, and the substrate to form a trench; forming a sidewall oxide layer on a sidewall and a bottom of the trench; forming a oxide layer liner including nitrogen on the sidewall oxide layer; and forming a gap fill layer on the oxide layer liner

Abstract translation: 一种制造半导体器件的方法，所述方法包括在衬底上依次形成衬垫氧化物层和氮化物层; 蚀刻氮化物层，衬垫氧化物层和衬底以形成沟槽; 在沟槽的侧壁和底部上形成侧壁氧化物层; 在所述侧壁氧化物层上形成包括氮的氧化物层衬垫; 并在氧化层衬垫上形成间隙填充层

公开(公告)号：US08697583B2

公开(公告)日：2014-04-15

申请号：US13224737

申请日：2011-09-02

Applicant: Kyung-seok Oh ,  Kyung-mun Byun ,  Shin-hye Kim ,  Deok-young Jung ,  Gil-heyun Choi ,  Eunkee Hong

Inventor： Kyung-seok Oh ,  Kyung-mun Byun ,  Shin-hye Kim ,  Deok-young Jung ,  Gil-heyun Choi ,  Eunkee Hong

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/76224

Abstract: Provided according to embodiments of the present invention are an oxidation-promoting compositions, methods of forming oxide layers, and methods of fabricating semiconductor devices. In some embodiments of the invention, the oxidation-promoting composition includes an oxidation-promoting agent having a structure of A-M-L, wherein L is a functional group that is chemisorbed to a surface of silicon, silicon oxide, silicon nitride, or metal, A is a thermally decomposable oxidizing functional group, and M is a moiety that allows A and L to be covalently bonded to each other.

Abstract translation: 根据本发明的实施方案提供的是氧化促进组合物，形成氧化物层的方法和制造半导体器件的方法。 在本发明的一些实施方案中，氧化促进组合物包括具有AML结构的氧化促进剂，其中L是化学吸附在硅表面，氧化硅，氮化硅或金属上的官能团，A是 一种可热分解的氧化官能团，M是允许A和L彼此共价结合的部分。

公开(公告)号：US20120058647A1

公开(公告)日：2012-03-08

申请号：US13224737

申请日：2011-09-02

Applicant: Kyung-seok Oh ,  Kyung-mun Byun ,  Shin-hye Kim ,  Deok-young Jung ,  Gil-heyun Choi ,  Eunkee Hong

Inventor： Kyung-seok Oh ,  Kyung-mun Byun ,  Shin-hye Kim ,  Deok-young Jung ,  Gil-heyun Choi ,  Eunkee Hong

IPC: H01L21/316

CPC classification number: H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/76224

Abstract: Provided according to embodiments of the present invention are an oxidation-promoting compositions, methods of forming oxide layers, and methods of fabricating semiconductor devices. In some embodiments of the invention, the oxidation-promoting composition includes an oxidation-promoting agent having a structure of A-M-L, wherein L is a functional group that is chemisorbed to a surface of silicon, silicon oxide, silicon nitride, or metal, A is a thermally decomposable oxidizing functional group, and M is a moiety that allows A and L to be covalently bonded to each other.

Abstract translation: 根据本发明的实施方案提供的是氧化促进组合物，形成氧化物层的方法和制造半导体器件的方法。 在本发明的一些实施方案中，氧化促进组合物包括具有AML结构的氧化促进剂，其中L是化学吸附在硅表面，氧化硅，氮化硅或金属上的官能团，A是 一种可热分解的氧化官能团，M是允许A和L彼此共价结合的部分。

公开(公告)号：US20090191687A1

公开(公告)日：2009-07-30

申请号：US12339125

申请日：2008-12-19

Applicant: Eunkee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek ,  Young-Sun Kim

Inventor： Eunkee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek ,  Young-Sun Kim

IPC: H01L21/76

CPC classification number: H01L21/76237 ,  H01L21/76232

Abstract: A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material.

Abstract translation: 在衬底中填充沟槽的方法确保在占据沟槽的材料中不留下空隙或接缝。 首先，形成预备绝缘层，以沿着沟槽的底部和侧面并且沿衬底的上表面连续延伸。 然后将杂质注入到与第一沟槽的顶部相邻的初级绝缘层的一部分中，以形成具有掺杂区域和未掺杂区域的第一绝缘层。 去除掺杂区域以在第一沟槽的底部和侧面形成第一绝缘层图案，并且该第一绝缘层图案限定第二沟槽。 然后用绝缘材料填充第二沟槽。