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    Semiconductor devices including 3-D structures with support pad structures and related methods and systems
    1.
    发明授权
    Semiconductor devices including 3-D structures with support pad structures and related methods and systems 有权
    包括具有支撑垫结构的3-D结构以及相关方法和系统的半导体器件

    公开(公告)号：US08624354B2

    公开(公告)日：2014-01-07

    申请号：US12829864

    申请日：2010-07-02

    申请人： Shin-hye Kim ,  Kyung-mun Byun ,  Hong-rae Kim ,  Gil-heyun Choi ,  Eun-kee Hong

    发明人： Shin-hye Kim ,  Kyung-mun Byun ,  Hong-rae Kim ,  Gil-heyun Choi ,  Eun-kee Hong

    IPC分类号： H01L21/02

    CPC分类号： H01L27/10817 ,  H01L27/10852 ,  H01L28/91

    摘要： A semiconductor device may include a semiconductor substrate and a plurality of three-dimensional capacitors on the semiconductor substrate. Each of the plurality of three-dimensional capacitors may include a first three-dimensional electrode, a capacitor dielectric layer, and a second three-dimensional electrode with the first three-dimensional electrode between the capacitor dielectric layer and the semiconductor substrate and with the capacitor dielectric layer between the first and second three-dimensional electrodes. A plurality of capacitor support pads may be provided with each capacitor support pad being arranged between adjacent first three-dimensional electrodes of adjacent three-dimensional capacitors with portions of the capacitor dielectric layers between the capacitor support pads and the semiconductor substrate. Related methods and apparatuses are also discussed.

    摘要翻译： 半导体器件可以包括半导体衬底和半导体衬底上的多个三维电容器。 多个三维电容器中的每一个可以包括第一三维电极，电容器电介质层和第二三维电极，其中在电容器介电层和半导体衬底之间具有第一三维电极，并且与电容器 第一和第二三维电极之间的介电层。 可以设置多个电容器支撑焊盘，每个电容器支撑焊盘布置在相邻的三维电容器的相邻的第一三维电极之间，其中电容器电介质层的一部分在电容器支撑焊盘和半导体衬底之间。 还讨论了相关的方法和装置。

    Methods of forming capacitors for semiconductor memory devices and resulting semiconductor memory devices
    3.
    发明授权
    Methods of forming capacitors for semiconductor memory devices and resulting semiconductor memory devices 失效
    形成用于半导体存储器件和所得半导体存储器件的电容器的方法

    公开(公告)号：US07459745B2

    公开(公告)日：2008-12-02

    申请号：US11866047

    申请日：2007-10-02

    申请人： Ju-Bum Lee ,  Shin-Hye Kim

    发明人： Ju-Bum Lee ,  Shin-Hye Kim

    IPC分类号： H01L27/108

    CPC分类号： H01L28/91 ,  H01L27/0207 ,  H01L27/10817 ,  H01L27/10852

    摘要： Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first interval. The storage electrodes are spaced apart from adjacent storage electrodes along a second direction oblique to the first direction by a second interval smaller than the first interval. First and second sacrificial layers are formed on the storage electrodes layer partially filling up a gap between adjacent storage electrodes along the first direction and filling up a gap between the adjacent storage electrodes along the second direction. Sacrificial spacers may be formed on sidewalls of the storage electrodes by etching the sacrificial layers. The second mold layer may be etched using the sacrificial spacers as etching masks to define a plurality of stabilizing structures. Resulting devices are also disclosed.

    摘要翻译： 形成电容器的方法包括在基板上形成第一模具层和第二模具层，通过模具层形成存储电极，沿着第一方向布置成沿着第一方向延伸并与相邻存储电极间隔开的行的存储电极， 第一个间隔。 存储电极沿着与第一方向相反的第二方向与相邻的存储电极隔开比第一间隔小的第二间隔。 第一牺牲层和第二牺牲层形成在沿着第一方向部分填充相邻存储电极之间的间隙的存储电极层上，并沿着第二方向填充相邻的存储电极之间的间隙。 通过蚀刻牺牲层，可以在存储电极的侧壁上形成牺牲性间隔物。 可以使用牺牲间隔物作为蚀刻掩模来蚀刻第二模具层，以限定多个稳定结构。 还公开了所产生的装置。

    Method of manufacturing a semiconductor device
    4.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07439150B2

    公开(公告)日：2008-10-21

    申请号：US11245367

    申请日：2005-10-05

    申请人： Shin-Hye Kim ,  Ju-Bum Lee ,  Min Kim

    发明人： Shin-Hye Kim ,  Ju-Bum Lee ,  Min Kim

    IPC分类号： H01L21/20

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91

    摘要： In one embodiment, to fabricate a semiconductor device, a first insulation interlayer is formed on a substrate. A contact pad is formed through the first insulation interlayer. An etch stop layer and a second insulation interlayer are sequentially formed on the first insulation interlayer and the pad. A contact hole exposing at least a portion of the contact pad is formed by partially etching the second insulation interlayer and the etch stop layer. A preliminary lower electrode is formed in the hole. The preliminary lower electrode is isotropically etched to form a lower electrode contacting the contact pad. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.

    摘要翻译： 在一个实施例中，为了制造半导体器件，在衬底上形成第一绝缘中间层。 通过第一绝缘夹层形成接触垫。 在第一绝缘夹层和衬垫上依次形成蚀刻停止层和第二绝缘中间层。 通过部分蚀刻第二绝缘夹层和蚀刻停止层来形成暴露接触焊盘的至少一部分的接触孔。 在孔中形成初级下电极。 预备下电极被各向同性地蚀刻以形成接触接触垫的下电极。 电介质层和上电极依次形成在下电极上。

    METHODS OF FORMING CAPACITORS FOR SEMICONDUCTOR MEMORY DEVICES AND RESULTING SEMICONDUCTOR MEMORY DEVICES
    5.
    发明申请
    METHODS OF FORMING CAPACITORS FOR SEMICONDUCTOR MEMORY DEVICES AND RESULTING SEMICONDUCTOR MEMORY DEVICES 审中-公开
    形成半导体存储器件和半导体存储器件的电容器的方法

    公开(公告)号：US20080026538A1

    公开(公告)日：2008-01-31

    申请号：US11866039

    申请日：2007-10-02

    申请人： Ju Lee ,  Shin-Hye Kim

    发明人： Ju Lee ,  Shin-Hye Kim

    IPC分类号： H01L21/02

    CPC分类号： H01L28/91 ,  H01L27/0207 ,  H01L27/10817 ,  H01L27/10852

    摘要： Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first interval. The storage electrodes are spaced apart from adjacent storage electrodes along a second direction oblique to the first direction by a second interval smaller than the first interval. First and second sacrificial layers are formed on the storage electrodes layer partially filling up a gap between adjacent storage electrodes along the first direction and filling up a gap between the adjacent storage electrodes along the second direction. Sacrificial spacers may be formed on sidewalls of the storage electrodes by etching the sacrificial layers. The second mold layer may be etched using the sacrificial spacers as etching masks to define a plurality of stabilizing structures. Resulting devices are also disclosed.

    摘要翻译： 形成电容器的方法包括在基板上形成第一模具层和第二模具层，通过模具层形成存储电极，沿着第一方向布置成沿着第一方向延伸并与相邻存储电极间隔开的行的存储电极， 第一个间隔。 存储电极沿着与第一方向相反的第二方向与相邻的存储电极隔开比第一间隔小的第二间隔。 第一牺牲层和第二牺牲层形成在沿着第一方向部分填充相邻存储电极之间的间隙的存储电极层上，并沿着第二方向填充相邻的存储电极之间的间隙。 通过蚀刻牺牲层，可以在存储电极的侧壁上形成牺牲性间隔物。 可以使用牺牲间隔物作为蚀刻掩模来蚀刻第二模具层，以限定多个稳定结构。 还公开了所产生的装置。

    Methods of forming capacitors for semiconductor memory devices and resulting semiconductor memory devices
    6.
    发明申请
    Methods of forming capacitors for semiconductor memory devices and resulting semiconductor memory devices 失效
    形成用于半导体存储器件和所得半导体存储器件的电容器的方法

    公开(公告)号：US20060033137A1

    公开(公告)日：2006-02-16

    申请号：US11195086

    申请日：2005-08-02

    申请人： Ju-Bum Lee ,  Shin-Hye Kim

    发明人： Ju-Bum Lee ,  Shin-Hye Kim

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L28/91 ,  H01L27/0207 ,  H01L27/10817 ,  H01L27/10852

    摘要： Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first interval. The storage electrodes are spaced apart from adjacent storage electrodes along a second direction oblique to the first direction by a second interval smaller than the first interval. First and second sacrificial layers are formed on the storage electrodes layer partially filling up a gap between adjacent storage electrodes along the first direction and filling up a gap between the adjacent storage electrodes along the second direction. Sacrificial spacers may be formed on sidewalls of the storage electrodes by etching the sacrificial layers. The second mold layer may be etched using the sacrificial spacers as etching masks to define a plurality of stabilizing structures. Resulting devices are also disclosed.

    摘要翻译： 形成电容器的方法包括在基板上形成第一模具层和第二模具层，通过模具层形成存储电极，沿着第一方向布置成沿着第一方向延伸并与相邻存储电极间隔开的行的存储电极， 第一个间隔。 存储电极沿着与第一方向相反的第二方向与相邻的存储电极隔开比第一间隔小的第二间隔。 第一牺牲层和第二牺牲层形成在沿着第一方向部分填充相邻存储电极之间的间隙的存储电极层上，并沿着第二方向填充相邻的存储电极之间的间隙。 通过蚀刻牺牲层，可以在存储电极的侧壁上形成牺牲性间隔物。 可以使用牺牲间隔物作为蚀刻掩模蚀刻第二模具层，以限定多个稳定结构。 还公开了所产生的装置。

    Method of manufacturing a semiconductor device
    8.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US06982223B2

    公开(公告)日：2006-01-03

    申请号：US10413944

    申请日：2003-04-15

    申请人： Ju-Wan Kim ,  Shin-Hye Kim ,  Ju-Bum Lee ,  Hyong-Soo Kim

    发明人： Ju-Wan Kim ,  Shin-Hye Kim ,  Ju-Bum Lee ,  Hyong-Soo Kim

    IPC分类号： H01L21/4763 ,  H01L21/31

    CPC分类号： H01L21/02129 ,  H01L21/02271 ,  H01L21/02315 ,  H01L21/02337 ,  H01L21/31625 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76837

    摘要： A method of manufacturing a semiconductor device by which a generation of a void is prevented after depositing an interlayer dielectric material. First, a plurality of conductive patterns are formed on a substrate and then, a capping insulation layer is formed on the conductive patterns. The capping insulation layer is treated with plasma, and an interlayer dielectric material is deposited on the plasma treated capping insulation layer. The dependency of the interlayer dielectric on the type of material and form of an underlying layer is reduced to improve a gap-filling characteristic, especially for a gap having a high aspect ratio. An improved gap-filling characteristic is accomplished and the formation of all or substantially all of the voids from forming in a gap is prevented even though an interlayer dielectric is deposited under a conventional deposition conditions.

    摘要翻译： 一种制造半导体器件的方法，其中在沉积层间电介质材料之后防止产生空隙。 首先，在基板上形成多个导电图案，然后在导电图案上形成封盖绝缘层。 用等离子体处理封盖绝缘层，并且在等离子体处理的封盖绝缘层上沉积层间电介质材料。 层间电介质对材料类型和下层的形式的依赖性被降低以改善间隙填充特性，特别是对于具有高纵横比的间隙。 实现了改进的间隙填充特性，并且即使在常规沉积条件下沉积层间电介质，也可防止在间隙中形成全部或基本上所有空隙的形成。

    Shallow trench isolation structure with converted liner layer
    9.
    发明授权
    Shallow trench isolation structure with converted liner layer 有权
    浅沟槽隔离结构具有转换内衬层

    公开(公告)号：US07163869B2

    公开(公告)日：2007-01-16

    申请号：US10947481

    申请日：2004-09-22

    申请人： Shin-Hye Kim ,  Min Kim ,  Seung-Jae Lee

    发明人： Shin-Hye Kim ,  Min Kim ,  Seung-Jae Lee

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224

    摘要： A STI (shallow trench isolation) structure is formed with a liner layer that is converted from an initial material to a subsequent material. For example, the liner layer is initially comprised of nitride during wet etch-back of a dielectric fill material comprised of oxide to protect an oxide layer on a semiconductor substrate. Thereafter, an exposed portion of the liner layer is converted into the subsequent material of oxide to protect the dielectric fill material within the STI opening during etching away of masking layers to prevent formation of dents in the STI structure.

    摘要翻译： STI（浅沟槽隔离）结构形成有从初始材料转换成后续材料的衬里层。 例如，在由氧化物构成的介电填充材料的湿法回蚀期间，衬垫层最初由氮化物组成，以保护半导体衬底上的氧化物层。 此后，衬里层的暴露部分被转换成随后的氧化物材料，以在蚀刻掉掩模层期间保护STI开口内的介电填充材料，以防止在STI结构中形成凹痕。

    Method of manufacturing a semiconductor device
    10.
    发明申请
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20060073669A1

    公开(公告)日：2006-04-06

    申请号：US11245367

    申请日：2005-10-05

    申请人： Shin-Hye Kim ,  Ju-Bum Lee ,  Min Kim

    发明人： Shin-Hye Kim ,  Ju-Bum Lee ,  Min Kim

    IPC分类号： H01L21/20

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91

    摘要： In one embodiment, to fabricate a semiconductor device, a first insulation interlayer is formed on a substrate. A contact pad is formed through the first insulation interlayer. An etch stop layer and a second insulation interlayer are sequentially formed on the first insulation interlayer and the pad. A contact hole exposing at least a portion of the contact pad is formed by partially etching the second insulation interlayer and the etch stop layer. A preliminary lower electrode is formed in the hole. The preliminary lower electrode is isotropically etched to form a lower electrode contacting the contact pad. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.

    摘要翻译： 在一个实施例中，为了制造半导体器件，在衬底上形成第一绝缘中间层。 通过第一绝缘夹层形成接触垫。 在第一绝缘夹层和衬垫上依次形成蚀刻停止层和第二绝缘中间层。 通过部分蚀刻第二绝缘夹层和蚀刻停止层来形成暴露接触焊盘的至少一部分的接触孔。 在孔中形成初级下电极。 预备下电极被各向同性地蚀刻以形成接触接触垫的下电极。 电介质层和上电极依次形成在下电极上。