公开(公告)号：US08624354B2

公开(公告)日：2014-01-07

申请号：US12829864

申请日：2010-07-02

申请人： Shin-hye Kim ,  Kyung-mun Byun ,  Hong-rae Kim ,  Gil-heyun Choi ,  Eun-kee Hong

发明人： Shin-hye Kim ,  Kyung-mun Byun ,  Hong-rae Kim ,  Gil-heyun Choi ,  Eun-kee Hong

IPC分类号： H01L21/02

CPC分类号： H01L27/10817 ,  H01L27/10852 ,  H01L28/91

摘要： A semiconductor device may include a semiconductor substrate and a plurality of three-dimensional capacitors on the semiconductor substrate. Each of the plurality of three-dimensional capacitors may include a first three-dimensional electrode, a capacitor dielectric layer, and a second three-dimensional electrode with the first three-dimensional electrode between the capacitor dielectric layer and the semiconductor substrate and with the capacitor dielectric layer between the first and second three-dimensional electrodes. A plurality of capacitor support pads may be provided with each capacitor support pad being arranged between adjacent first three-dimensional electrodes of adjacent three-dimensional capacitors with portions of the capacitor dielectric layers between the capacitor support pads and the semiconductor substrate. Related methods and apparatuses are also discussed.

摘要翻译： 半导体器件可以包括半导体衬底和半导体衬底上的多个三维电容器。 多个三维电容器中的每一个可以包括第一三维电极，电容器电介质层和第二三维电极，其中在电容器介电层和半导体衬底之间具有第一三维电极，并且与电容器 第一和第二三维电极之间的介电层。 可以设置多个电容器支撑焊盘，每个电容器支撑焊盘布置在相邻的三维电容器的相邻的第一三维电极之间，其中电容器电介质层的一部分在电容器支撑焊盘和半导体衬底之间。 还讨论了相关的方法和装置。

公开(公告)号：US20110207334A1

公开(公告)日：2011-08-25

申请号：US12902212

申请日：2010-10-12

申请人： Yong-soon CHOI ,  Hong-gun KIM ,  Ha-young YI ,  Gil-heyun CHOI ,  Eun-kee Hong

发明人： Yong-soon CHOI ,  Hong-gun KIM ,  Ha-young YI ,  Gil-heyun CHOI ,  Eun-kee Hong

IPC分类号： H01L21/31

CPC分类号： H01L21/02126 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/76224

摘要： A method of manufacturing a semiconductor device includes an improved technique of filling a trench to provide the resulting semiconductor device with better characteristics and higher reliability. The method includes forming a trench in a semiconductor layer, forming a first layer on the semiconductor layer using a silicon source and a nitrogen source to fill the trench, curing the first layer using an oxygen source, and annealing the second layer. The method may also be used to form other types of insulating layers such as an interlayer insulating layer.

摘要翻译： 一种制造半导体器件的方法包括一种填充沟槽的改进技术，以使得到的半导体器件具有更好的特性和更高的可靠性。 该方法包括在半导体层中形成沟槽，使用硅源和氮源在半导体层上形成第一层以填充沟槽，使用氧源固化第一层，并退火第二层。 该方法也可用于形成其它类型的绝缘层，例如层间绝缘层。

公开(公告)号：US20090045483A1

公开(公告)日：2009-02-19

申请号：US12222630

申请日：2008-08-13

申请人： Sang-Ho Rha ,  Eun-Kee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek

发明人： Sang-Ho Rha ,  Eun-Kee Hong ,  Kyung-Mun Byun ,  Jong-Wan Choi ,  Eun-Kyung Baek

IPC分类号： H01L21/762 ,  H01L23/58

CPC分类号： H01L21/76232

摘要： A semiconductor device may include a semiconductor substrate, trench region, buffer pattern, gap fill layer, and transistor. The trench region may be provided in the semiconductor substrate to define an active region. The buffer pattern and gap fill layer may be provided in the trench region. The buffer pattern and gap fill layer may fill the trench region. The gap fill layer may be densified by the buffer pattern. The transistor may be provided in the active region. A method of manufacturing a semiconductor device may include: forming a trench region in a semiconductor substrate; forming a buffer layer on an inner wall of the first trench region; forming a gap fill layer, filling the trench region; performing a thermal process to react the impurity with the oxygen, forming a buffer pattern; and forming a transistor in the active region.

摘要翻译： 半导体器件可以包括半导体衬底，沟槽区，缓冲图案，间隙填充层和晶体管。 沟槽区域可以设置在半导体衬底中以限定有源区域。 缓冲图案和间隙填充层可以设置在沟槽区域中。 缓冲图案和间隙填充层可以填充沟槽区域。 间隙填充层可以由缓冲图案致密化。 晶体管可以设置在有源区中。 半导体器件的制造方法可以包括：在半导体衬底中形成沟槽区域; 在所述第一沟槽区的内壁上形成缓冲层; 形成间隙填充层，填充沟槽区域; 进行热处理以使杂质与氧反应，形成缓冲图案; 以及在有源区中形成晶体管。

公开(公告)号：US20050026443A1

公开(公告)日：2005-02-03

申请号：US10631848

申请日：2003-08-01

申请人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Kyu-Tae Na

发明人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Kyu-Tae Na

IPC分类号： H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L21/02222 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02343 ,  H01L21/3125 ,  H01L21/3165 ,  H01L21/76229 ,  H01L21/76826 ,  H01L21/76828

摘要： A method is provided for forming silicon oxide layers during the processing of semiconductor devices by applying a SOG layer including polysilazane to a substrate and then substantially converting the SOG layer to a silicon oxide layer using an oxidant solution. The oxidant solution may include one or more oxidants including, for example, ozone, peroxides, permanganates, hypochlorites, chlorites, chlorates, perchlorates, hypobromites, bromites, bromates, hypoiodites, iodites, iodates and strong acids.

摘要翻译： 提供了一种通过将包含聚硅氮烷的SOG层施加到衬底然后使用氧化剂溶液将SOG层基本上转化为氧化硅层来在半导体器件加工期间形成氧化硅层的方法。 氧化剂溶液可以包括一种或多种氧化剂，包括例如臭氧，过氧化物，高锰酸盐，次氯酸盐，亚氯酸盐，氯酸盐，高氯酸盐，次溴酸盐，溴酸盐，溴酸盐，次碘酸盐，碘酸盐，碘酸盐和强酸。

公开(公告)号：US06645879B2

公开(公告)日：2003-11-11

申请号：US10215309

申请日：2002-08-08

申请人： Eun-Kee Hong ,  Ju-Bum Lee ,  Ju-Seon Goo ,  Myeong-Cheol Kim ,  Hong-Gun Kim

发明人： Eun-Kee Hong ,  Ju-Bum Lee ,  Ju-Seon Goo ,  Myeong-Cheol Kim ,  Hong-Gun Kim

IPC分类号： H01L2131

CPC分类号： H01L21/76897 ,  H01L21/31051 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76834 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  Y10S438/935 ,  H01L2924/00

摘要： Disclosed are methods for forming a silicon oxide layer of a semiconductor device capable of insulating between fine conductive patterns without causing a process failure, and for forming a wiring having the silicon oxide layer. After forming conductive patterns on a semiconductor substrate, an anti-oxidation layer is sequentially formed on the conductive patterns and on the semiconductor substrate. The anti-oxidation layer prevents an oxidant from penetrating into the conductive patterns and the semiconductor substrate. A reflowable oxide layer is formed by coating a reflowable oxidizing material on the anti-oxidation layer while burying the conductive patterns. The silicon oxide layer is formed by thermally treating the reflowable oxide layer. Then, the silicon oxide layer filled between conductive patterns and the anti-oxidation layer exposed to the semiconductor substrate are etched so as to form a contact hole, thereby forming the wiring of the semiconductor device. Thus, a planar silicon oxide layer is formed between conductive patterns having a fine interval therebetween without creating a void. In addition, a metal layer pattern, which acts as a conductor in the conductive patterns, can be prevented from being oxidized when the silicon oxide layer is formed.

摘要翻译： 公开了用于形成能够在不导致工艺故障的细导电图案之间绝缘的半导体器件的氧化硅层的形成方法，以及用于形成具有氧化硅层的布线的方法。 在半导体衬底上形成导电图案之后，在导电图案和半导体衬底上依次形成抗氧化层。 抗氧化层防止氧化剂渗透到导电图案和半导体衬底中。 通过在抗氧化层上涂覆可回流氧化材料同时掩埋导电图案来形成可回流氧化物层。 通过热处理可回流氧化物层形成氧化硅层。 然后，在导电图案和暴露于半导体基板的抗氧化层之间填充的氧化硅层被蚀刻以形成接触孔，从而形成半导体器件的布线。 因此，在其间具有微细间隔的导电图案之间形成平面氧化硅层，而不产生空隙。 此外，当形成氧化硅层时，可以防止在导电图案中充当导体的金属层图案被氧化。

公开(公告)号：US08530329B2

公开(公告)日：2013-09-10

申请号：US13162050

申请日：2011-06-16

申请人： Yong-Soon Choi ,  Jun-Won Lee ,  Gil-Heyun Choi ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Ha-Young Yi

发明人： Yong-Soon Choi ,  Jun-Won Lee ,  Gil-Heyun Choi ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Ha-Young Yi

IPC分类号： H01L21/78

CPC分类号： H01L21/76229 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11531 ,  H01L27/11548

摘要： A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.

摘要翻译： 制造半导体器件的方法包括在半导体衬底中形成第一沟槽和第二沟槽，形成第一绝缘体以完全填充第一沟槽，第一绝缘体覆盖第二沟槽的底表面和下侧壁，并暴露上侧壁 并且在所述第二沟槽中的所述第一绝缘体上形成第二绝缘体。

公开(公告)号：US20070117412A1

公开(公告)日：2007-05-24

申请号：US11656469

申请日：2007-01-23

申请人： Ju-seon Goo ,  Eun-kee Hong ,  Hong-Gun Kim ,  Kyu-tae Na

发明人： Ju-seon Goo ,  Eun-kee Hong ,  Hong-Gun Kim ,  Kyu-tae Na

IPC分类号： H01L21/31

CPC分类号： H01L21/02222 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02343 ,  H01L21/3125 ,  H01L21/3165 ,  H01L21/76229 ,  H01L21/76826 ,  H01L21/76828

摘要： A method is provided for forming silicon oxide layers during the processing of semiconductor devices by applying a SOG layer including polysilazane to a substrate and then substantially converting the SOG layer to a silicon oxide layer using an oxidant solution. The oxidant solution may include one or more oxidants including, for example, ozone, peroxides, permanganates, hypochlorites, chlorites, chlorates, perchlorates, hypobromites, bromites, bromates, hypoiodites, iodites, iodates and strong acids.

摘要翻译： 提供了一种通过将包含聚硅氮烷的SOG层施加到衬底然后使用氧化剂溶液将SOG层基本上转化为氧化硅层来在半导体器件加工期间形成氧化硅层的方法。 氧化剂溶液可以包括一种或多种氧化剂，包括例如臭氧，过氧化物，高锰酸盐，次氯酸盐，亚氯酸盐，氯酸盐，高氯酸盐，次溴酸盐，溴酸盐，溴酸盐，次碘酸盐，碘酸盐，碘酸盐和强酸。

公开(公告)号：US06762126B2

公开(公告)日：2004-07-13

申请号：US10082019

申请日：2002-02-20

申请人： Young-Joo Cho ,  Eun-Kee Hong ,  Ju-Bum Lee

发明人： Young-Joo Cho ,  Eun-Kee Hong ,  Ju-Bum Lee

IPC分类号： H01L21311

CPC分类号： H01L21/02222 ,  H01L21/02164 ,  H01L21/02318 ,  H01L21/02337 ,  H01L21/3125

摘要： In a method for forming an interlayer dielectric film, an insulating film is deposited on a semiconductor substrate that has a metal wiring pattern. The insulating film is polished by CMP until exposing an upper portion of the wiring pattern. A spin on glass composition, which includes polysilazane, is coated over the polished insulating material and exposed portions of the wiring pattern to form a film. The film is then pre-baked in a temperature range of 50 to 350° C., and then hard-baked in a temperature range of 300 to 500° C. After the hard-baking, the film is then heat-treated in an oxidation atmosphere. With the hard-baking, gasses of the coating of film may be removed so that the amount of gas generated during a subsequent anneal or heat-treating process may be reduced. Accordingly, particle contaminants may be reduced by such process in addition to providing a means for reduced risk of crack formation.

摘要翻译： 在形成层间电介质膜的方法中，在具有金属布线图案的半导体基板上沉积绝缘膜。 通过CMP抛光绝缘膜，直到暴露布线图案的上部。 包括聚硅氮烷在内的旋涂玻​​璃组合物涂覆在抛光的绝缘材料上并且布线图案的暴露部分形成膜。 然后将膜在50〜350℃的温度范围内进行预烘烤，然后在300〜500℃的温度范围内进行硬烘烤。在硬烘烤后，将膜进行热处理 氧化气氛。 通过硬烘烤，可以除去膜涂层的气体，从而可以减少在随后的退火或热处理过程中产生的气体的量。 因此，除了提供降低裂纹风险的方法之外，还可以通过这种方法减少颗粒污染物。

公开(公告)号：US06635586B2

公开(公告)日：2003-10-21

申请号：US09977673

申请日：2001-10-15

申请人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Jin-Gi Hong

发明人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Jin-Gi Hong

IPC分类号： H01L2469

CPC分类号： H01L21/02282 ,  H01L21/02123 ,  H01L21/02222 ,  H01L21/02337 ,  H01L21/316 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76837

摘要： A method of forming a SOG insulation layer of a semiconductor device comprises forming the SOG insulation layer on a substrate having a stepped pattern by using a polysilazane in a solution state, performing a pre-bake process for removing solvent elements of the insulation layer at a temperature of 50 to 350° C., performing a hard bake process for restraining particles from forming at a temperature of 350 to 500° C., and annealing at a temperature of 600 to 1200° C. The method of the invention further includes planarizing the insulation layer between the hard bake process and the annealing step. Also, the hard bake process can be omitted.

摘要翻译： 形成半导体器件的SOG绝缘层的方法包括：通过使用溶液状态的聚硅氮烷在具有阶梯状图案的基板上形成SOG绝缘层，进行用于除去绝缘层的溶剂元素的预烘烤工序 温度为50〜350℃，进行用于抑制微粒在350〜500℃的温度下形成的硬烘烤工艺，在600〜1200℃的温度下进行退火。本发明的方法还包括平面化 硬烘烤工艺与退火步骤之间的绝缘层。 此外，可以省略硬烘焙处理。

公开(公告)号：US07517817B2

公开(公告)日：2009-04-14

申请号：US11656469

申请日：2007-01-23

申请人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Kyu-Tae Na

发明人： Ju-Seon Goo ,  Eun-Kee Hong ,  Hong-Gun Kim ,  Kyu-Tae Na

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02222 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02343 ,  H01L21/3125 ,  H01L21/3165 ,  H01L21/76229 ,  H01L21/76826 ,  H01L21/76828

摘要： A method is provided for forming silicon oxide layers during the processing of semiconductor devices by applying a SOG layer including polysilazane to a substrate and then substantially converting the SOG layer to a silicon oxide layer using an oxidant solution. The oxidant solution may include one or more oxidants including, for example, ozone, peroxides, permanganates, hypochlorites, chlorites, chlorates, perchlorates, hypobromites, bromites, bromates, hypoiodites, iodites, iodates and strong acids.

摘要翻译： 提供了一种通过将包含聚硅氮烷的SOG层施加到衬底然后使用氧化剂溶液将SOG层基本上转化为氧化硅层来在半导体器件加工期间形成氧化硅层的方法。 氧化剂溶液可以包括一种或多种氧化剂，包括例如臭氧，过氧化物，高锰酸盐，次氯酸盐，亚氯酸盐，氯酸盐，高氯酸盐，次溴酸盐，溴酸盐，溴酸盐，次碘酸盐，碘酸盐，碘酸盐和强酸。