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    Methods for forming openings with improved aspect ratios in integrated circuit devices, and related structures
    3.
    发明授权
    Methods for forming openings with improved aspect ratios in integrated circuit devices, and related structures 失效
    用于在集成电路器件中形成具有改进的纵横比的开口的方法以及相关结构

    公开(公告)号：US5942803A

    公开(公告)日：1999-08-24

    申请号：US819601

    申请日：1997-03-17

    申请人： Myoung-seob Shim ,  Hun-chul Shin ,  Kyung-seok Oh

    发明人： Myoung-seob Shim ,  Hun-chul Shin ,  Kyung-seok Oh

    IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/48

    CPC分类号： H01L21/76804 ,  H01L21/76807

    摘要： A method for forming an opening in an integrated circuit device with an improved aspect ratio includes the following steps. An inter-insulating layer is formed on a surface of a substrate. A recess having a first width is then formed in the inter-insulating layer. Next, a hole having a second width is formed in the inter-insulating layer at a base of the recess, wherein the first width is greater than the second width. Thus, an opening is formed to have a cross-sectional shape of a step where its upper portion formed by the recess which is wider than its lower portion formed by the hole. Accordingly, open circuits caused by voids formed in the opening in subsequent metal deposition steps may be prevented.

    摘要翻译： 在具有改进的纵横比的集成电路器件中形成开口的方法包括以下步骤。 在基板的表面上形成绝缘层。 然后在绝缘层中形成具有第一宽度的凹部。 接下来，在凹部的基部的绝缘层中形成具有第二宽度的孔，其中，第一宽度大于第二宽度。 因此，开口形成为具有由凹部形成的上部比其由孔形成的下部更宽的台阶的截面形状。 因此，可以防止在随后的金属沉积步骤中在开口中形成的空隙引起的开路。

    CMOS integrated circuits including source/drain plug
    5.
    发明授权
    CMOS integrated circuits including source/drain plug 失效
    CMOS集成电路包括源极/漏极插头

    公开(公告)号：US06274914B1

    公开(公告)日：2001-08-14

    申请号：US08855024

    申请日：1997-05-13

    申请人： Young-hoon Park ,  Yang-koo Lee ,  Kyung-seok Oh

    发明人： Young-hoon Park ,  Yang-koo Lee ,  Kyung-seok Oh

    IPC分类号： H01L2980

    CPC分类号： H01L27/0928

    摘要： A CMOS integrated circuit includes an NMOS transistor and a PMOS transistor in an integrated circuit substrate. The NMOS transistor and the PMOS transistor each include a gate, and a source/drain on opposing sides of the gate. An insulating layer is located on the integrated circuit substrate. The insulating layer includes a contact hole therein which exposes a portion of a corresponding one of the source/drains. A source/drain plug is formed in the corresponding one of the source/drains. The source/drain plug is of opposite conductivity from the corresponding one of the source/drains. The source/drain plug is centered about the portion of the corresponding one of the source/drains. The source/drain plug may be formed by ion implantation through the contact hole and is thereby self-aligned to the contact hole. The source/drain plug can compensate for misalignment and the diffusion for highly integrated CMOS devices.

    摘要翻译： CMOS集成电路在集成电路基板中包括NMOS晶体管和PMOS晶体管。 NMOS晶体管和PMOS晶体管各自包括栅极，栅极的相对侧上的源极/漏极。 绝缘层位于集成电路基板上。 绝缘层包括其中暴露出源极/漏极中的相应一个的一部分的接触孔。 源/排水塞形成在相应的一个源/排水管中。 源极/漏极插塞与源极/漏极中相应的一个相反。 源极/漏极插头以相应的一个源极/漏极的部分为中心。 源极/漏极插塞可以通过接触孔的离子注入形成，从而与接触孔自对准。 源极/漏极插头可以补偿高度集成的CMOS器件的不对准和扩散。

    Methods for fabricating CMOS integrated circuits including source/drain compensating regions
    7.
    发明授权
    Methods for fabricating CMOS integrated circuits including source/drain compensating regions 有权

    公开(公告)号：US06423589B1

    公开(公告)日：2002-07-23

    申请号：US09885432

    申请日：2001-06-20

    申请人： Young-hoon Park ,  Yang-koo Lee ,  Kyung-seok Oh

    发明人： Young-hoon Park ,  Yang-koo Lee ,  Kyung-seok Oh

    IPC分类号： H01L21828

    摘要： A CMOS integrated circuit includes an NMOS transistor and a PMOS transistor in an integrated circuit substrate. The NMOS transistor and the PMOS transistor each include a gate, and a source/drain on opposing sides of the gate. An insulating layer is located on the integrated circuit substrate. The insulating layer includes a contact hole therein which exposes a portion of a corresponding one of the source/drains. A source/drain plug is formed in the corresponding one of the source/drains. The source/drain plug is of opposite conductivity from the corresponding one of the source/drains. The source/drain plug is centered about the portion of the corresponding one of the source/drains. The source/drain plug may be formed by ion implantation through the contact hole and is thereby self-aligned to the contact hole. The source/drain plug can compensate for misalignment and the diffusion for highly integrated CMOS devices.

    Method for forming contact holes having different depths
    8.
    发明授权
    Method for forming contact holes having different depths 失效
    形成不同深度的接触孔的方法

    公开(公告)号：US5444020A

    公开(公告)日：1995-08-22

    申请号：US135495

    申请日：1993-10-13

    申请人： Seung-ku Lee ,  Kyung-seok Oh

    发明人： Seung-ku Lee ,  Kyung-seok Oh

    IPC分类号： G03F1/70 ,  G03F1/80 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L21/44

    CPC分类号： H01L21/76804 ,  H01L21/76802 ,  H01L21/76807 ,  Y10S148/051

    摘要： A method for forming contact holes having different depths in an insulating layer which covers a semiconductor substrate. A first step selectively etches the upper parts of the insulating layer which correspond to contact holes having a greater depth than the shallowest contact hole, using a first mask pattern. A second etch step selectively etches the remainder of the insulating layer for all of the contact holes at the same time using a second mask pattern. Thus, contact hole misalignment is kept to a minimum.

    摘要翻译： 一种在覆盖半导体衬底的绝缘层中形成具有不同深度的接触孔的方法。 使用第一掩模图案，第一步骤选择性地蚀刻对应于具有比最浅接触孔更深的接触孔的绝缘层的上部。 第二蚀刻步骤使用第二掩模图案同时选择性地蚀刻所有接触孔的绝缘层的剩余部分。 因此，接触孔未对准被保持最小。