公开(公告)号：US20150022985A1

公开(公告)日：2015-01-22

申请号：US14331419

申请日：2014-07-15

Applicant: KYUNG-TAE NA ,  CHUL-WOO KIM ,  BOK-SIK MYUNG ,  SEUNG-HWAN LEE

Inventor： KYUNG-TAE NA ,  CHUL-WOO KIM ,  BOK-SIK MYUNG ,  SEUNG-HWAN LEE

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/183 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/3511 ,  H05K1/113 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012

Abstract: A package substrate includes a core layer having a core top surface and a core bottom surface, and a build-up layer having a stacked structure in which a plurality of interconnection layers and a plurality of insulating layers are alternately stacked on the core top surface. The core bottom surface includes a board connecting area. A surface of the build-up layer includes a chip mounting area. The core layer includes at least one cavity defined by recess sidewalls extending upward from the core bottom surface and a recessed surface located at a higher level than or the same level as the core top surface, at least one device mounted in the at least one cavity, and through-electrodes electrically connecting the core top surface and the core bottom surface.

Abstract translation: 封装基板包括具有芯顶表面和芯底表面的芯层，以及堆叠结构，其中多个互连层和多个绝缘层交替堆叠在芯顶表面上。 芯底表面包括板连接区域。 堆积层的表面包括芯片安装区域。 芯层包括由从芯底表面向上延伸的凹陷侧壁和位于与芯顶表面相比高于或相同高度的凹陷表面限定的至少一个空腔，至少一个装置安装在至少一个腔 ，以及将芯顶表面和芯底表面电连接的通孔。

公开(公告)号：US20140091463A1

公开(公告)日：2014-04-03

申请号：US13943037

申请日：2013-07-16

Applicant: Hae-jung YU ,  Hak-kyoon BYUN ,  Kyung-tae NA ,  Seung-hun HAN ,  Tae-sung PARK ,  Choong-bin YIM

Inventor： Hae-jung YU ,  Hak-kyoon BYUN ,  Kyung-tae NA ,  Seung-hun HAN ,  Tae-sung PARK ,  Choong-bin YIM

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: According to example embodiments of inventive concepts, a semiconductor package apparatus includes a first semiconductor package including a first substrate, a first solder resist layer on the first substrate, and a first sealing member that covers and protects the first solder resist layer, and a plurality of solder balls on the first substrate. The plurality of solder balls includes a first solder ball having a first height and a second solder ball having a second height that is different from the first height. The first sealing member includes holes that expose the solder balls.

Abstract translation: 根据发明构思的示例性实施例，半导体封装装置包括第一半导体封装，其包括第一衬底，第一衬底上的第一阻焊层和覆盖并保护第一阻焊层的第一密封构件，以及多个 的焊球在第一基板上。 多个焊球包括具有第一高度的第一焊球和具有与第一高度不同的第二高度的第二焊球。 第一密封构件包括露出焊球的孔。