公开(公告)号：US5365204A

公开(公告)日：1994-11-15

申请号：US145364

申请日：1993-10-29

申请人： John M. Angiulli ,  Arun K. Ghose ,  Richard R. Konian ,  Samuel R. Levine ,  David Meltzer ,  Wen-Yuan Wang ,  Leon L. Wu

发明人： John M. Angiulli ,  Arun K. Ghose ,  Richard R. Konian ,  Samuel R. Levine ,  David Meltzer ,  Wen-Yuan Wang ,  Leon L. Wu

IPC分类号： H03K3/03 ,  H03K3/354 ,  H03B5/24

CPC分类号： H03K3/354 ,  H03K3/0315

摘要： A variable frequency digital ring oscillator which can be formed in a small area for use in testing of chips employs a ring oscillator formed of CMOS inverters, transmission gates and capacitors and CMOS logic as a voltage controlled ring oscillator. A wide range of frequency of oscillation is achieved with small number of components. The ring oscillator circuit's oscillator frequency is controlled only by DC voltages, such as may be provided by (but not limited to) a manufacturing chip tester. The output signal of the oscillator swings between Vdd and Vss and does not need additional level translation circuits to drive CMOS logic. The ring oscillator can be composed of an odd number of CMOS inverters connected in cascade to form a loop. We provide a CMOS transmission gate with PMOS and NMOS transistor device inserted between each adjacent inverter and a MOS capacitor connected between the output of each transmission gate and the Vss supply of the ring oscillator circuit (conventionally ground). The gate voltages of the PMOS and NMOS transistors in the transmission gate are different and provide a different DC voltage between Vdd and Vss. Variation of the gate voltages of the transmission gates controls the frequency of oscillation of the circuit. The use of a plurality of cascaded delay elements between inverters achieves a wider range of oscillation frequency than possible with a single delay element.

摘要翻译： 可以形成在用于芯片测试的小区域中的可变频数字环形振荡器采用由CMOS反相器，传输门和电容器形成的环形振荡器和作为压控环形振荡器的CMOS逻辑。 通过少量组件实现了宽范围的振荡。 环形振荡器电路的振荡器频率仅由直流电压控制，例如可以由（但不限于）制造芯片测试器提供。 振荡器的输出信号在Vdd和Vss之间摆动，不需要额外的电平转换电路来驱动CMOS逻辑。 环形振荡器可以由串联连接的奇数CMOS反相器组成，形成一个环路。 我们提供一个CMOS传输门，PMOS和NMOS晶体管器件插在每个相邻的反相器和连接在每个传输门的输出和环形振荡器电路的Vss电源（传统接地）之间的MOS电容器。 传输门中PMOS和NMOS晶体管的栅极电压不同，并在Vdd和Vss之间提供不同的直流电压。 传输门的栅极电压的变化控制电路的振荡频率。 在逆变器之间使用多个级联延迟元件实现比单个延迟元件可能的更宽的振荡频率范围。

公开(公告)号：US4035607A

公开(公告)日：1977-07-12

申请号：US634695

申请日：1976-03-19

申请人： Leon L. Wu

发明人： Leon L. Wu

IPC分类号： B41J2/34 ,  H05B1/00

CPC分类号： B41J2/34

摘要： A thermal display comprising an array of semiconductor heater mesas having a larger cross-sectional area at the display surface than at the support surface. The preferred structure is in the shape of a truncated, inverted pyramid. The novel method includes forming the inverted heater elements by etching trenches in one surface of the semiconductor substrate and forming the heater mesas at the opposite surface, with the trenches defining the individual mesas.

摘要翻译： 一种热显示器，包括在显示表面处比在支撑表面处具有较大横截面面积的半导体加热器台面阵列。 优选的结构是截头倒置的金字塔的形状。 新颖的方法包括通过在半导体衬底的一个表面中蚀刻沟槽并在相对的表面形成加热器台面来形成倒置的加热器元件，其中沟槽限定各个台面。

公开(公告)号：US11074522B2

公开(公告)日：2021-07-27

申请号：US16916013

申请日：2020-06-29

申请人： Roger N. Anderson ,  Boyi Xie ,  Leon L. Wu ,  Arthur Kressner

发明人： Roger N. Anderson ,  Boyi Xie ,  Leon L. Wu ,  Arthur Kressner

IPC分类号： G06N20/00

摘要： Electric Grid Analytics Learning Machine, EGALM, is a machine learning based, “brutally empirical” analysis system for use in all energy operations. EGALM is applicable to all aspects of the electricity operations from power plants to homes and businesses. EGALM is a data-centric, computational learning and predictive analysis system that uses open source algorithms and unique techniques applicable to all electricity operations in the United States and other foreign countries.

公开(公告)号：US6104629A

公开(公告)日：2000-08-15

申请号：US156134

申请日：1998-09-17

申请人： Leon L. Wu

发明人： Leon L. Wu

IPC分类号： H01L25/065 ,  G11C5/06

CPC分类号： G11C5/06

摘要： Memory chips (15) are mounted perpendicularly on a memory module substrate (14) to achieve a close spacing between the chips. A plurality of memory chip signal lines (20) are located on the memory module substrate (14) and the memory chips (15) are electrically coupled to the memory chip signal lines at spaced apart chip coupling points (23). Digital signals are driven to the memory chip signal lines (20) through signal lines (21) having a first level impedance. The memory chip signal lines (20) have a second level impedance greater that the first level impedance. The spacing between the chip coupling points (23) is chosen such that the effective impedance level of the memory chip signal lines (20) substantially matches the lower, first level impedance.

摘要翻译： 存储芯片（15）垂直地安装在存储器模块基板（14）上，以实现芯片之间的紧密间隔。 多个存储器芯片信号线（20）位于存储器模块基板（14）上，并且存储芯片（15）在间隔开的芯片耦合点（23）处电耦合到存储芯片信号线。 通过具有第一电平阻抗的信号线（21）将数字信号驱动到存储器芯片信号线（20）。 存储器芯片信号线（20）具有比第一电平阻抗更大的第二电平阻抗。 选择芯片耦合点（23）之间的间隔使得存储芯片信号线（20）的有效阻抗水平基本上与较低的第一电平阻抗匹配。

公开(公告)号：US5754399A

公开(公告)日：1998-05-19

申请号：US954208

申请日：1992-09-30

申请人： Leon L. Wu

发明人： Leon L. Wu

IPC分类号： G06F1/18 ,  H05H7/20

CPC分类号： G06F1/183

摘要： An improved packaging scheme for a CPU of a main frame computer improves the performance while at the same reduces the cost of manufacture of the main frame computer. A single packaging technology is used to package the whole CPU and eliminates cable connections inside the CPU. Surface power bus technology permits the fabrication of a module with chips mounted on both front and back sides of the substrate. The surface power bus is installed on one or both sides of the module surface and derives power directly from the power cable and distributes power to chip sites directly. In a specific implementation, a uni-processor CPU with chips mounted on both surfaces of the substrate and power fed from the surface power bus results in improved processor package density and system performance. The direct coupling between the high performance processor CPU and a high cost performance ratio ceramic board not only eliminates a great portion of hardware but also reduces a significant portion of the memory path and channel path delays.

摘要翻译： 用于主框架计算机的CPU的改进的封装方案提高了性能，同时降低了主机计算机的制造成本。 单一封装技术用于封装整个CPU，并消除了CPU内部的电缆连接。 表面电力总线技术允许制造具有安装在基板的前后两侧的芯片的模块。 表面电源总线安装在模块表面的一侧或两侧，直接从电源线导出电源，并直接将电源分配给芯片。 在具体实现中，具有安装在基板的两个表面上的芯片的单处理器CPU和从表面电源总线馈送的电力导致改进的处理器封装密度和系统性能。 高性能处理器CPU和高成本性能比陶瓷板之间的直接耦合不仅消除了大部分硬件，而且减少了存储器路径和通道路径延迟的很大一部分。

公开(公告)号：US4803595A

公开(公告)日：1989-02-07

申请号：US129404

申请日：1987-11-25

申请人： Charles J. Kraus ,  Leon L. Wu

发明人： Charles J. Kraus ,  Leon L. Wu

IPC分类号： H01L23/538 ,  H01L23/64 ,  H05K1/18

CPC分类号： H01L23/5385 ,  H01L23/5382 ,  H01L23/642 ,  H01L2224/16

摘要： Engineering changes in the wiring between semiconductor device chips supported on the same substrate are made using minimum substrate real estate and without the use of engineering change pads or discrete wires by the use of easily modified chip interposers. The interposers are inserted between respective chips and the substrate. The interposers comprise conductive vias and multiple internal wiring planes which are selectively connected to the vias.

摘要翻译： 支持在同一基板上的半导体器件芯片之间的布线的工程变化是使用最小的衬底空间来制造的，并且通过使用易于修改的芯片插入件而不使用工程改变焊盘或分立的导线。 插入件插入在相应的芯片和基板之间。 内插件包括有选择地连接到通孔的导电通路和多个内部布线平面。

公开(公告)号：US4535388A

公开(公告)日：1985-08-13

申请号：US626359

申请日：1984-06-29

申请人： Charles J. Kraus ,  Herbert I. Stoller ,  Leon L. Wu

发明人： Charles J. Kraus ,  Herbert I. Stoller ,  Leon L. Wu

IPC分类号： H05K3/46 ,  H01L23/538 ,  H05K1/00 ,  H05K1/11

CPC分类号： H01L23/5383 ,  H05K1/115 ,  H01L2224/16225 ,  H05K1/0289 ,  H05K2201/09609 ,  H05K3/4629

摘要： The wiring nets on a module are divided into two groups of planes, i.e., an upper group in which wiring is placed along "north-south" and "east-west" directions and a lower group in which wiring is placed along diagonal directions. All vias for connecting to the wiring pass through the upper group of planes but only half of the vias pass through the lower group of planes. Thus the spacing between the vias of the lower group of planes is greater than the spacing between the upper vias, allowing more lines per wiring channel in the lower group of planes.

摘要翻译： 模块上的接线网被分成两组平面，即沿着“南北”和“东西”方向放置布线的上组，以及沿着对角方向布置布线的下组。 用于连接到接线的所有通孔都穿过上层平面，但只有一半通孔穿过下层的平面。 因此，下组平面的通孔之间的间距大于上通孔之间的间隔，从而允许下层组中的每个布线通道更多的线。

公开(公告)号：US3953264A

公开(公告)日：1976-04-27

申请号：US501567

申请日：1974-08-29

申请人： Leon L. Wu

发明人： Leon L. Wu

IPC分类号： H01C7/00 ,  B41J2/34 ,  H01L21/822 ,  H01L27/04 ,  H04N1/032 ,  H01L21/22 ,  H01L21/306

CPC分类号： B41J2/34 ,  Y10S438/969

摘要： A thermal display heater elements array for a comprising an array of semiconductor heater mesas having a larger cross-sectional area at the display surface than at the support surface. The preferred structure is in the shape of a truncated, inverted pyramid. The novel method includes forming the inverted heater elements by etching trenches in one surface of the semiconductor substrate and forming the heater mesas at the opposite surface, with the trenches defining the individual mesas.

摘要翻译： 一种用于包括在显示表面处比在支撑表面处具有较大横截面面积的半导体加热器台面阵列的热显示加热器元件阵列。 优选的结构是截头倒置的金字塔的形状。 新颖的方法包括通过在半导体衬底的一个表面中蚀刻沟槽并在相对的表面形成加热器台面来形成倒置的加热器元件，其中沟槽限定各个台面。

公开(公告)号：US20200334577A1

公开(公告)日：2020-10-22

申请号：US16916013

申请日：2020-06-29

申请人： ROGER N. ANDERSON ,  BOYI XIE ,  LEON L. WU ,  ARTHUR KRESSNER

发明人： ROGER N. ANDERSON ,  BOYI XIE ,  LEON L. WU ,  ARTHUR KRESSNER

IPC分类号： G06N20/00

摘要： Electric Grid Analytics Learning Machine, EGALM, is a machine learning based, “brutally empirical” analysis system for use in all energy operations. EGALM is applicable to all aspects of the electricity operations from power plants to homes and businesses. EGALM is a data-centric, computational learning and predictive analysis system that uses open source algorithms and unique techniques applicable to all electricity operations in the United States and other foreign countries.

公开(公告)号：US5362986A

公开(公告)日：1994-11-08

申请号：US109230

申请日：1993-08-19

申请人： John M. Angiulli ,  Eugene S. Kolankowsky ,  Richard R. Konian ,  Leon L. Wu

发明人： John M. Angiulli ,  Eugene S. Kolankowsky ,  Richard R. Konian ,  Leon L. Wu

IPC分类号： H01L23/12 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/10 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L25/18 ,  H01L25/0652 ,  H01L2924/0002 ,  Y10T29/49144

摘要： A packaging substrate (10) is populated with memory chip cube(s) (40) and horizontally mounted interconnect chip(s) (19)mounted on the substrate which are joined during assembly using two kinds of lead tin solder alloys to form the memory chip cube. One is a high melting point lead tin alloy (HMA), another is a lower melting point lead tin alloy (LMA). The memory chip pairs (11) of the memory cube are formed by placing functional memory chips over other functional memory chips before they were diced. The chip pads of the individual memory chips and the lead tin pads of the memory chips within the wafer are aligned and the high melting point lead tin solder is reflowed, forming memory chip pairs.

摘要翻译： 封装基板（10）上安装有安装在基板上的存储芯片立方体（40）和水平安装的互连芯片（19），其在组装期间使用两种铅锡焊料合金接合以形成存储器 芯片立方体。 一种是高熔点铅锡合金（HMA），另一种是低熔点铅锡合金（LMA）。 存储器立方体的存储器芯片组（11）通过在切割之前将功能存储器芯片放置在其它功能存储器芯片上而形成。 单个存储器芯片的芯片焊盘和晶片内的存储器芯片的引线锡焊盘对准，并且高熔点铅锡焊料回流，形成存储器芯片对。