公开(公告)号：US20130026560A1

公开(公告)日：2013-01-31

申请号：US13575984

申请日：2011-01-28

申请人： Yasuhiko Onishi ,  Mutsumi Kitamura ,  Akio Sugi ,  Manabu Takei

发明人： Yasuhiko Onishi ,  Mutsumi Kitamura ,  Akio Sugi ,  Manabu Takei

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7813

摘要： A parallel p-n layer (20) is provided as a drift layer between an active portion and an n+ drain region (11). The parallel p-n layer (20) is formed by an n-type region (1) and a p-type region (2) being repeatedly alternately joined. An n-type high concentration region (21) is provided on a first main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration higher than that of an n-type low concentration region (22) provided on a second main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (22). Also, the n-type high concentration region (21) has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region (1) adjacent to the p-type region (2).

摘要翻译： 在活性部分和n +漏极区域（11）之间提供平行p-n层（20）作为漂移层。 平行p-n层（20）由n型区域（1）和重复交替接合的p型区域（2）形成。 n型高浓度区域（21）设置在n型区域（1）的第一主表面侧。 n型高浓度区域（21）的杂质浓度高于设置在n型区域（1）的第二主面侧的n型低浓度区域（22）的杂质浓度。 n型高浓度区域（21）的杂质浓度比n型低浓度区域（22）的杂质浓度大1.2倍以上3倍以下，优选为1.5倍以上2.5倍以下。 此外，n型高浓度区域（21）的n区域（1）的相邻区域的厚度的三分之一以下，优选为八分之一以上，四分之一以下。 p型区域（2）。

公开(公告)号：US08362980B2

公开(公告)日：2013-01-29

申请号：US13010624

申请日：2011-01-20

申请人： Manabu Takei ,  Tomoyuki Shirasaki ,  Ikuhiro Yamaguchi ,  Tsuyoshi Ozaki ,  Jun Ogura

发明人： Manabu Takei ,  Tomoyuki Shirasaki ,  Ikuhiro Yamaguchi ,  Tsuyoshi Ozaki ,  Jun Ogura

IPC分类号： G09G3/30

CPC分类号： G09G3/325 ,  G09G3/3266 ,  G09G3/3283 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2310/0216 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/027

摘要： A display device includes a display panel having a plurality of signal lines and scanning lines with a plurality of display pixels containing current control type light emitting devices; a scan driver circuit which applies a scanning signal to each of the scanning lines and sets the display pixels connected to the scanning lines in a selective state; a signal driver circuit which generates gradation current based on a display data luminosity gradation component and supplies to the display pixels set in the selective state; a precharge circuit which applies a precharge voltage to each signal line and sets a capacity component attached to each of the scanning lines in a predetermined charged state; and an operation control circuit which controls setting of the light emitting devices in a non-light emitting state when the capacity component is set in a predetermined charged state.

摘要翻译： 显示装置包括具有多个信号线的显示面板和具有包含电流控制型发光装置的多个显示像素的扫描线; 扫描驱动器电路，其将扫描信号施加到每条扫描线，并将连接到扫描线的显示像素设置在选择状态; 信号驱动器电路，其基于显示数据亮度灰度分量生成灰度电流，并提供给以选择状态设置的显示像素; 预充电电路，对每个信号线施加预充电电压，并且以预定的充电状态设置附接到每条扫描线的电容分量; 以及操作控制电路，当电容分量被设定在预定的充电状态时，控制发光器件在非发光状态下的设置。

公开(公告)号：US08339384B2

公开(公告)日：2012-12-25

申请号：US12569322

申请日：2009-09-29

申请人： Manabu Takei ,  Jun Ogura ,  Shunji Kashiyama ,  Tsuyoshi Ozaki

发明人： Manabu Takei ,  Jun Ogura ,  Shunji Kashiyama ,  Tsuyoshi Ozaki

IPC分类号： G06F3/038

CPC分类号： G09G3/3233 ,  G09G3/30 ,  G09G3/3291 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2320/0233 ,  G09G2320/0285 ,  G09G2320/0295 ,  G09G2320/043

摘要： A data acquisition circuit sets one of the potential value at one end of a signal line and the value of a current flown thereto when one end of a current path of a drive device is connected to a light emitting device with the other end thereof set to a potential value where no current flows to the light emitting device. Then the circuit causes current to flow via the current path and the signal line and acquires one of the value of the current flown to the signal line and the potential value at the one end of the signal line according to the set value. A correction operation circuit acquires a threshold voltage and a current amplification factor of the drive device based on one of the current and potential values thus acquired as well as on one of the potential and current values thus set.

摘要翻译： 数据采集​​电路将驱动装置的电流路径的一端连接到发光装置的另一端设定为信号线的一端的电位值中的一方和流过的电流值 没有电流流向发光器件的电位值。 然后，电路使电流通过电流路径和信号线流动，并根据设定值获取流向信号线的电流值和信号线一端的电位值之一。 校正操作电路基于如此获取的电流和电位值之一以及由此设置的电势值和电流值之一获取驱动装置的阈值电压和电流放大系数。

公开(公告)号：US20120184083A1

公开(公告)日：2012-07-19

申请号：US13352581

申请日：2012-01-18

申请人： Kazuo SHIMOYAMA ,  Manabu TAKEI ,  Haruo NAKAZAWA

发明人： Kazuo SHIMOYAMA ,  Manabu TAKEI ,  Haruo NAKAZAWA

IPC分类号： H01L21/78

CPC分类号： H01L29/7393 ,  H01L21/30608 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/7395 ,  H01L2221/68327 ,  H01L2221/68381

摘要： A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate. Then, on the wafer, a trench to become a scribing line is formed with a crystal face exposed so as to form a side wall of the trench. On that side wall, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to dice a collector electrode, formed on the p collector region, together with the p collector region.

摘要翻译： 在其上形成有形成半导体芯片的顶表面结构和底表面结构的薄半导体晶片被固定到支撑衬底。 然后，在晶片上形成成为划线的沟槽，其上露出一个晶面以形成沟槽的侧壁。 在该侧壁上，通过离子注入和低温退火或激光退火形成用于保持反向击穿电压的隔离层，以便在与作为底表面扩散层的ap集电极区域接触的同时延伸到顶表面侧 。 然后，进行激光切割以与p收集区一起形成在集电极区上形成的集电极。

公开(公告)号：US08138542B2

公开(公告)日：2012-03-20

申请号：US12427322

申请日：2009-04-21

申请人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

发明人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

IPC分类号： H01L29/76 ,  H01L21/20

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

摘要翻译： 公开了一种包括n型半导体衬底，p型沟道区和设置在n型半导体衬底和p型沟道区之间的结层的半导体器件。 接合层具有与n型半导体衬底的主表面平行的方向交替布置的n型漂移区和p型隔离区。 形成结层的p型分隔区的杂质浓度比n型漂移区高。 这使得半导体器件具有增强的击穿电压，并且同时具有降低的导通电阻。

公开(公告)号：US07863151B2

公开(公告)日：2011-01-04

申请号：US12489884

申请日：2009-06-23

申请人： Manabu Takei

发明人： Manabu Takei

IPC分类号： H01L21/76

CPC分类号： H01L29/66712 ,  H01L23/544 ,  H01L29/0634 ,  H01L29/66136 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.

摘要翻译： 用于制造超结半导体器件的制造方法在表现出低电阻的n型半导体衬底上表现出高电阻的n型外延层上形成氧化物膜和氮化物膜。 划线区域中的氮化物膜的部分通过图案化而不被去除，并且通过氮化物膜打开取向标记。 在氧化物膜中打开沟槽图案之后，形成具有高纵横比的沟槽。 去除划线区域外部的氧化膜部分，将p型外延层埋设在沟槽中。 相对于氮化物膜研磨过度生长的p型外延层，通过蚀刻来完成研磨表面，露出n型外延层表面。

公开(公告)号：US07741192B2

公开(公告)日：2010-06-22

申请号：US11208459

申请日：2005-08-19

申请人： Kazuo Shimoyama ,  Manabu Takei ,  Haruo Nakazawa

发明人： Kazuo Shimoyama ,  Manabu Takei ,  Haruo Nakazawa

IPC分类号： H01L21/76

CPC分类号： H01L29/7393 ,  H01L21/30608 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/7395 ,  H01L2221/68327 ,  H01L2221/68381

摘要： A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer. Thereafter, the double-sided adhesive tape is removed from the collector electrode to produce semiconductor chips. A highly reliable reverse-blocking semiconductor device can thus be formed at a low cost.

摘要翻译： 形成半导体芯片的上表面结构和底面结构的薄半导体晶片通过双面胶带固定在支撑基板上。 然后，在薄半导体晶片上，通过湿式各向异性蚀刻形成成为划刻线的沟槽，其中晶体面被暴露以形成沟槽的侧壁。 在具有如此露出的晶面的沟槽的侧壁上，通过离子注入和低温退火或激光退火形成用于保持反向击穿电压的隔离层，以便在与...接触的同时延伸到顶表面侧 ap集电极区域作为底面扩散层。 然后，进行激光切割，与集电体区域一起形成在集电极区域上的集电极整齐地切割，而不会在隔离层下方产生任何过量的部分和不足的部分。 此后，从集电极去除双面胶带以制造半导体芯片。 因此可以以低成本形成高度可靠的反向阻挡半导体器件。

公开(公告)号：US20100134475A1

公开(公告)日：2010-06-03

申请号：US12626747

申请日：2009-11-27

申请人： JUN OGURA ,  Manabu Takei ,  Shunji Kashiyama

发明人： JUN OGURA ,  Manabu Takei ,  Shunji Kashiyama

IPC分类号： G06F3/038

CPC分类号： G09G3/3291 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2320/04

摘要： A pixel driving device has a voltage impressing circuit that outputs a reference voltage that exceeds a threshold voltage of a drive transistor, a voltage measurement circuit, and a property parameter acquisition circuit that acquires a property parameter related to an electronic property of a pixel. The pixel driving device impresses the reference voltage on the pixel that has a light emitting element and the drive transistor. The voltage measurement circuit acquires voltage of a signal line, as measured voltages, after each of a plurality of the settling times elapsing from the time when the reference voltage is cut. The property parameter acquisition circuit acquires, as property parameters, the threshold voltage and a current amplification factor of drive transistor based on values of a plurality of measured voltages acquired by the voltage measurement circuit.

摘要翻译： 像素驱动装置具有输出超过驱动晶体管的阈值电压的参考电压的电压施加电路，电压测量电路和获取与像素的电子特性相关的特性参数的属性参数获取电路。 像素驱动装置对具有发光元件的像素和驱动晶体管施加参考电压。 在从基准电压切断时起经过的多个稳定时间的每一个之后，电压测量电路获取作为测量电压的信号线的电压。 属性参数获取电路基于由电压测量电路获取的多个测量电压的值作为特性参数获取驱动晶体管的阈值电压和电流放大系数。

公开(公告)号：US20100134469A1

公开(公告)日：2010-06-03

申请号：US12626752

申请日：2009-11-27

申请人： JUN OGURA ,  Manabu Takei ,  Shunji Kashiyama

发明人： JUN OGURA ,  Manabu Takei ,  Shunji Kashiyama

IPC分类号： G09G5/00

CPC分类号： G09G3/3291 ,  G09G3/3233 ,  G09G2300/0842 ,  G09G2320/043

摘要： A light emitting device has a plurality of pixels, each of which includes a drive transistor, a light emitting element and signal lines, a property parameter acquisition circuit which acquires property parameter, a signal correction circuit that generates a corrected gradation signal by correcting the image data based on the property parameter, and a drive signal impressing circuit that impresses a drive signal, generated based on the corrected gradation signal, on the pixel to drive it. The property parameter is constituted of a threshold voltage, a current amplification factor and its irregularity of the drive transistor, and is acquired based on measured voltages of the signal lines after each of a plurality of predetermined settling times elapses from the time when the light emitting device cuts off a voltage subsequent to impressing the voltage on each pixel for a predetermined length of time.

摘要翻译： 发光器件具有多个像素，每个像素包括驱动晶体管，发光元件和信号线，获取特性参数的属性参数获取电路，通过校正图像产生校正灰度信号的信号校正电路 基于属性参数的数据，以及驱动信号施加电路，其将基于校正灰度信号生成的驱动信号压印在像素上以驱动该驱动信号。 属性参数由阈值电压，电流放大系数及其驱动晶体管的不规则度构成，并且是从发光时起经过多个预定建立时间之后经过的信号线的测量电压而获取的 器件在每个像素上施加电压达预定时间之后切断电压。

公开(公告)号：US20100093164A1

公开(公告)日：2010-04-15

申请号：US12575730

申请日：2009-10-08

申请人： Haruo NAKAZAWA ,  Kazuo SHIMOYAMA ,  Manabu TAKEI

发明人： Haruo NAKAZAWA ,  Kazuo SHIMOYAMA ,  Manabu TAKEI

IPC分类号： H01L21/22

CPC分类号： H01L29/0661 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/66333 ,  H01L29/7395

摘要： On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips. With such a manufacturing method, a reverse-blocking semiconductor device having high reliability can be formed.

摘要翻译： 在薄的半导体晶片的顶表面上形成形成半导体芯片的顶表面结构。 晶片的上表面用双面胶带固定在支撑基板上。 然后，从薄的半导体晶片的底面开始，通过湿式各向异性蚀刻形成成为刻划线的沟槽，使得沟槽的侧壁露出。 在暴露了晶面的沟槽的侧壁上，通过离子注入与底面扩散层的集电极区域同时形成具有不同于用于保持反向击穿电压的半导体晶片的导电类型的隔离层， 然后用激光照射退火。 侧壁形成大致V形或梯形形状的横截面，侧壁相对于支撑基底的角度为30-70°。 然后从上表面去除双面胶带以制造半导体芯片。 通过这样的制造方法，可以形成具有高可靠性的反向阻挡半导体器件。