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1.发明申请METHOD OF TEST OF CLOCK GENERATION CIRCUIT IN ELECTRONIC DEVICE, AND ELECTRONIC DEVICE 失效电子设备中的时钟发生电路的测试方法和电子设备公开(公告)号：US20070233411A1
公开(公告)日：2007-10-04
申请号：US11487504
申请日：2006-07-17
CPC分类号： G01R31/31727
摘要： In an electronic device having an interface circuit which operates using a fast clock source, frequency deviation of the clock source is inspected in the mounted state. The clock pulses of the fast clock source are counted in synchronization with an electronic device serving as reference, and the result is checked; or, alignment data of transfer data and overflow/underflow of the FIFO buffer are utilized; or, the count values of an internal counter and a fast clock counter are utilized, to check for frequency deviation of the fast clock source. In the state of being mounted in the device, tests can be performed of the clock sources of all units.
摘要翻译： 在具有使用快速时钟源工作的接口电路的电子设备中，在安装状态下检查时钟源的频率偏差。 快速时钟源的时钟脉冲与作为参考的电子设备同步计数，并检查结果; 或者使用FIFO缓冲器的传送数据和溢出/下溢的对准数据; 或者使用内部计数器和快速时钟计数器的计数值来检查快速时钟源的频率偏差。 在安装在设备中的状态下，可以对所有单元的时钟源进行测试。
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2.发明授权Disk apparatus for detecting position of head by reading phase servo pattern 失效用于通过读取相位伺服模式来检测头部的位置的盘装置
公开(公告)号：US5694265A
公开(公告)日：1997-12-02
申请号：US298052
申请日：1994-08-30
CPC分类号： G11B5/596
摘要： A duty pulse is formed by setting in response to a leading edge of a clock synchronized with a peak detection of a servo frame read signal by a peak detecting circuit and by resetting by a signal by which a zero-cross point of a read signal of a phase servo pattern was detected. A head position signal is formed by integrating the duty pulse. Since there is a deviation of the timings between the peak detection and the zero-cross detection, a duty ratio is measured so as to be adjusted to 50% in the on-track state of a target cylinder. The timings for a reference clock and a zero-cross detection pulse are delayed and adjusted accordingly.
摘要翻译： 通过响应于与由峰值检测电路的伺服帧读取信号的峰值检测同步的时钟的前沿设置响应于占空比脉冲，并且通过将信号的读取信号的零交叉点 检测到相位伺服模式。 通过对占空比脉冲进行积分来形成头位置信号。 由于峰值检测和过零检测之间的定时存在偏差，因此在目标气缸的导轨状态下测量占空比以便调整为50％。 参考时钟和零交叉检测脉冲的定时被相应地延迟和调整。
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3.发明申请公开(公告)号：US20060082918A1
公开(公告)日：2006-04-20
申请号：US11043492
申请日：2005-01-25
申请人： Tatsuhiko Kosugi , Masahide Kanegae
发明人： Tatsuhiko Kosugi , Masahide Kanegae
CPC分类号： G11B5/59633 , G11B5/59666 , G11B27/36 , G11B2220/20
摘要： An information storage apparatus that records servo information and user data on a recording face of a recording medium wherein a track density measuring unit measures the optimal track density for a recording face corresponding to each head targeting a storage medium on which the servo information has not yet been recorded and a recording density measuring unit measures the optimal linear density for each recording face. A servo frame writing unit writes the servo information varying a track pitch to a track pitch corresponding to the optimal track density measured by the track density measuring unit and a recording frequency to a recording frequency corresponding to the optimal linear density measured by the linear density measuring unit, for each head.
摘要翻译： 一种信息存储装置，其将伺服信息和用户数据记录在记录介质的记录面上，其中轨道密度测量单元测量与针对其上还存在伺服信息的存储介质的每个磁头相对应的记录面的最佳磁道密度 记录密度测量单元测量每个记录面的最佳线密度。 伺服帧写入单元将将轨道间距改变为对应于由轨道密度测量单元测量的最佳轨道密度的轨道音调和记录频率的伺服信息写入对应于通过线性密度测量测量的最佳线性密度的记录频率 单位，每个头。
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公开(公告)号：US5841602A
公开(公告)日：1998-11-24
申请号：US715040
申请日：1996-09-17
申请人： Masahide Kanegae , Masao Kondou
发明人： Masahide Kanegae , Masao Kondou
CPC分类号： G11B27/3027 , G11B20/10009 , G11B20/1488 , H04L25/061 , G11B2005/0018 , H04L7/041 , H04L7/044
摘要： Disclosed is a PRML regenerating apparatus for regenerating a signal read by a head from a storage medium. This PRML regenerating apparatus has a waveform equalizing circuit for waveform-equalizing the read signal, a maximum-likelihood decoder for maximum-likelihood-decoding, after obtaining a determination value by comparing the equalized output with upper and lower slice levels, this determination value and a control circuit for setting variable a distance between the upper slice level and the lower slice level of the maximum-likelihood decoder. The distance between the upper and lower slice levels can be thereby set variable in accordance with an equalization characteristic. A ternary determination circuit of the maximum-likelihood decoder is constructed of a memory for storing a correspondence table of the equalized output and the upper or lower slice level versus the determination result and the next upper or lower slice level. The ternary determination circuit can be thereby actualized with a simple configuration.
摘要翻译： 公开了一种用于从存储介质再生由头读取的信号的PRML再生装置。 该PRML再生装置具有用于使读取信号波形均衡的波形均衡电路，用于最大似然解码的最大似然解码器，在通过将均衡输出与上限和下限电平进行比较而获得确定值之后，该确定值和 控制电路，用于设定最大似然解码器的上限位电平和下限电平之间的距离。 因此，可以根据均衡特性将上限和下限电平之间的距离设置为可变的。 最大似然解码器的三元确定电路由用于存储均衡输出和上限或下限电平的对应表与存储器相关的确定结果和下一个上限或下限电平构成。 因此可以用简单的结构实现三元确定电路。
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5.发明授权
公开(公告)号：US5825570A
公开(公告)日：1998-10-20
申请号：US714351
申请日：1996-09-16
申请人： Masahide Kanegae , Masao Kondou , Tomoki Sugaya , Hiroyuki Tanaka
发明人： Masahide Kanegae , Masao Kondou , Tomoki Sugaya , Hiroyuki Tanaka
CPC分类号： G11B27/3027 , G11B20/10009 , G11B20/1488 , H04L25/061 , G11B2005/0018 , H04L7/041 , H04L7/044
摘要： Disclosed is a PRML regenerating apparatus for regenerating a signal read by a head from a storage medium. This PRML regenerating apparatus has a waveform equalizing circuit for waveform-equalizing the read signal, a maximum-likelihood decoder for maximum-likelihood-decoding, after obtaining a determination value by comparing the equalized output with upper and lower slice levels, this determination value and a control circuit for setting variable a distance between the upper slice level and the lower slice level of the maximum-likelihood decoder. The distance between the upper and lower slice levels can be thereby set variable in accordance with an equalization characteristic. A ternary determination circuit of the maximum-likelihood decoder is constructed of a memory for storing a correspondence table of the equalized output and the upper or lower slice level versus the determination result and the next upper or lower slice level. The ternary determination circuit can be thereby actualized with a simple configuration.
摘要翻译： 公开了一种用于从存储介质再生由头读取的信号的PRML再生装置。 该PRML再生装置具有用于使读取信号波形均衡的波形均衡电路，用于最大似然解码的最大似然解码器，在通过将均衡输出与上限和下限电平进行比较而获得确定值之后，该确定值和 控制电路，用于设定最大似然解码器的上限位电平和下限电平之间的距离。 因此，可以根据均衡特性将上限和下限电平之间的距离设置为可变的。 最大似然解码器的三元确定电路由用于存储均衡输出和上限或下限电平的对应表与存储器相关的确定结果和下一个上限或下限电平构成。 因此可以用简单的结构实现三元确定电路。
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6.发明申请公开(公告)号：US20110317302A1
公开(公告)日：2011-12-29
申请号：US13048297
申请日：2011-03-15
申请人： Yuji SAKAI , Kazuhito SHIMOMURA , Masahide KANEGAE
发明人： Yuji SAKAI , Kazuhito SHIMOMURA , Masahide KANEGAE
IPC分类号： G11B27/36
CPC分类号： G11B5/6029 , G11B5/607
摘要： According to one embodiment, a disk storage apparatus includes a read module, a measuring module, and a compensating module. The read module is configured to read first and second signals recorded on a disk, from which to measure the flying height of a head. The measuring module is configured to calculate the flying height of the head from the first and second measurement signals read by the read module. The compensating module is configured to use the data representing the flying height representing error resulting from superparamagnetic effect, thereby compensating for the flying height measured by the measuring module.
摘要翻译： 根据一个实施例，盘存储装置包括读取模块，测量模块和补偿模块。 读取模块被配置为读取记录在盘上的第一和第二信号，以测量头的飞行高度。 测量模块被配置为从读取模块读取的第一和第二测量信号计算头部的飞行高度。 补偿模块被配置为使用表示由超顺磁效应导致的飞行高度的数据，从而补偿由测量模块测量的飞行高度。
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7.发明授权Method of test of clock generation circuit in electronic device, and electronic device 失效电子设备中时钟发生电路的测试方法和电子设备公开(公告)号：US07272527B1
公开(公告)日：2007-09-18
申请号：US11487504
申请日：2006-07-17
IPC分类号： G01M19/00
CPC分类号： G01R31/31727
摘要： In an electronic device having an interface circuit which operates using a fast clock source, frequency deviation of the clock source is inspected in the mounted state. The clock pulses of the fast clock source are counted in synchronization with an electronic device serving as reference, and the result is checked; or, alignment data of transfer data and overflow/underflow of the FIFO buffer are utilized; or, the count values of an internal counter and a fast clock counter are utilized, to check for frequency deviation of the fast clock source. In the state of being mounted in the device, tests can be performed of the clock sources of all units.
摘要翻译： 在具有使用快速时钟源工作的接口电路的电子设备中，在安装状态下检查时钟源的频率偏差。 快速时钟源的时钟脉冲与作为参考的电子设备同步计数，并检查结果; 或者使用FIFO缓冲器的传送数据和溢出/下溢的对准数据; 或者使用内部计数器和快速时钟计数器的计数值来检查快速时钟源的频率偏差。 在安装在设备中的状态下，可以对所有单元的时钟源进行测试。
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公开(公告)号：US6021025A
公开(公告)日：2000-02-01
申请号：US824167
申请日：1997-03-26
CPC分类号： G11B5/486 , G11B21/083 , H05K3/361
摘要： An actuator for moving heads in a disk unit having heads for reading or writing data from or on recording surfaces of disks driven to rotate, an actuator having arms for supporting the heads, a main FPC board having one end thereof supported by the actuator and the other end thereof supported by a body of the disk unit, and relay FPC boards placed along the arms of the actuator, which can realize a compact and thin size, resistive to noise, and permitting a reduction in manufacturing cost. A printed-circuit board is supported by an actuator, is electrically connected to a circuit unit in a body of a disk unit via a main FPC board, and is electrically connected to heads via relay FPC boards. Integrated circuits are mounted on the printed-circuit board.
摘要翻译： 一种驱动器，用于在具有用于从被驱动旋转的盘的记录表面上读取或写入数据的磁头的磁盘单元，具有用于支撑磁头的臂的致动器，其一端由致动器支撑的主FPC板和 其另一端由盘单元的主体支撑，以及沿着致动器的臂放置的中继FPC板，其可以实现紧凑而薄的尺寸，耐噪声，并且允许降低制造成本。 印刷电路板由致动器支撑，经由主FPC板电连接到盘单元的主体中的电路单元，并通过中继FPC板与头电连接。 集成电路安装在印刷电路板上。
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公开(公告)号：US5689655A
公开(公告)日：1997-11-18
申请号：US777398
申请日：1996-12-27
申请人： Hiroyuki Tanaka , Masahide Kanegae
发明人： Hiroyuki Tanaka , Masahide Kanegae
CPC分类号： G06F13/4081 , G06F13/4086
摘要： An apparatus for connecting and disconnecting a plurality of drives connected in parallel with respect to a data transmission line in a magnetic disk system, etc., to and from the data transmission line under an active state, has data communication terminals provided for each of the drives, so as to be connected to the data transmission line and disconnected from the data transmission line; and units for fixing the levels at the data communication terminals when the data communication terminals are open. Preferably, the units for fixing the levels includes resistors connected between the data communication terminals and a ground, the resistance of each of the resistors being determined not to disturb an impedance of the data transmission line.
摘要翻译： 一种用于在激活状态下连接和断开与数据传输线中的数据传输线并联连接的多个驱动器的装置，具有为每个驱动器提供的数据通信终端 驱动器，以便连接到数据传输线并与数据传输线断开连接; 以及用于在数据通信终端打开时固定数据通信终端的电平的单元。 优选地，用于固定电平的单元包括连接在数据通信端子和地之间的电阻器，每个电阻器的电阻被确定为不干扰数据传输线路的阻抗。
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10.发明授权Data reproducing circuit for memory system having an equalizer generating two different equalizing signals used for data reproduction 失效具有生成用于数据复制的两个不同均衡信号的均衡器的存储器系统的数据再生电路
公开(公告)号：US5068753A
公开(公告)日：1991-11-26
申请号：US323943
申请日：1989-03-15
申请人： Masahide Kanegae
发明人： Masahide Kanegae
CPC分类号： G11B20/10046 , G11B20/10009 , G11B5/035
摘要： A data recording and reproducing circuit for a memory system, such as a magnetic disk memory system. The circuit includes a reflection type cosine equalizer and a data reproducing circuit. The equalizer includes a first equalizing circuit, having a first equalizing gain, and outputting a first equalized signal, and a second equalizing circuit having a second equalizing gain smaller than the first equalizing gain, and outputting a second equalizing circuit. The data reproducing circuit includes a differentiator for differentiating the first equalized signal, a window generating circuit for generating a window signal from the second equalized signal, and a data separator for discriminating the differentiated signal in response to the window signal to produce a pulsed reproduction signal.
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