公开(公告)号：US08816419B2

公开(公告)日：2014-08-26

申请号：US12665584

申请日：2008-06-17

申请人： Masaru Takaishi

发明人： Masaru Takaishi

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66666 ,  H01L29/7803 ,  H01L29/7828 ,  H01L29/7831 ,  H01L29/7839

摘要： Provided is a semiconductor device having a high switching speed. A semiconductor device is provided with an n-type epitaxial layer having a plurality of trenches arranged at prescribed intervals; an embedded electrode formed on an inner surface of the trench through a silicon oxide film to embed each trench; and a metal layer, which is capacitively coupled with the embedded electrode by being arranged above the embedded electrode through a silicon oxide film. In the semiconductor device, a region between the adjacent trenches operates as a channel (current path). A current flowing in the channel is interrupted by covering the region with a depletion layer formed at the periphery of the trenches, and the current is permitted to flow through the channel by eliminating the depletion layer at the periphery of the trenches.

摘要翻译： 提供了具有高开关速度的半导体器件。 半导体器件设置有具有以规定间隔布置的多个沟槽的n型外延层; 嵌入电极，其通过氧化硅膜形成在沟槽的内表面上，以嵌入每个沟槽; 以及金属层，其通过在氧化硅膜上配置在嵌入电极的上方而与嵌入电极电容耦合。 在半导体器件中，相邻沟槽之间的区域作为沟道（电流路径）起作用。 通过用形成在沟槽周边的耗尽层覆盖区域来中断在沟道中流动的电流，并且通过消除沟槽周边的耗尽层，允许电流流过沟道。

公开(公告)号：US08766317B2

公开(公告)日：2014-07-01

申请号：US12665538

申请日：2008-06-17

申请人： Masaru Takaishi

发明人： Masaru Takaishi

IPC分类号： H01L29/66

CPC分类号： H01L29/7391 ,  H01L29/7302 ,  H01L29/739

摘要： Provided is a semiconductor device in which on-resistance is largely reduced based on a new principle of operation. In the semiconductor device, if an embedded electrode is at negative potential, a depletion layer is formed from a trench to a neighboring trench so that a channel is turned off. If the embedded electrode is at a positive potential, the depletion layer is not formed in every region between the neighboring trenches so that the channel is turned on.

摘要翻译： 提供了一种基于新的操作原理，导通电阻大大降低的半导体器件。 在半导体器件中，如果嵌入电极处于负电位，则从沟槽到相邻的沟槽形成耗尽层，使得沟道截止。 如果嵌入电极处于正电位，则在相邻沟槽之间的每个区域中不形成耗尽层，以使通道导通。

公开(公告)号：US20100193837A1

公开(公告)日：2010-08-05

申请号：US12665538

申请日：2008-06-17

申请人： Masaru Takaishi

发明人： Masaru Takaishi

IPC分类号： H01L29/739

CPC分类号： H01L29/7391 ,  H01L29/7302 ,  H01L29/739

摘要： Provided is a semiconductor device in which on-resistance is largely reduced based on a new principle of operation. In the semiconductor device (1), if an embedded electrode (5) is at negative potential, a depletion layer (11) is formed from a trench (3a) to a neighboring trench so that a channel (10) is turned off. If the embedded electrode is at a positive potential, the depletion layer is not formed in every region between the neighboring trenches so that the channel is turned on.

摘要翻译： 提供了一种基于新的操作原理，导通电阻大大降低的半导体器件。 在半导体器件（1）中，如果嵌入电极（5）处于负电位，则从沟槽（3a）到相邻的沟槽形成耗尽层（11），使得沟道（10）截止。 如果嵌入电极处于正电位，则在相邻沟槽之间的每个区域中不形成耗尽层，以使通道导通。

公开(公告)号：US20100176447A1

公开(公告)日：2010-07-15

申请号：US12601923

申请日：2008-05-30

申请人： Masaru Takaishi

发明人： Masaru Takaishi

IPC分类号： H01L29/78

CPC分类号： H01L29/7828 ,  H01L29/0619 ,  H01L29/7839

摘要： Provided is a semiconductor device in which on-resistance is largely reduced. The semiconductor device includes an n type epitaxial layer (2) in which each region between neighboring trenches (3) becomes a channel (9), and a plurality of embedded electrodes (5) each of which is formed on an inner surface of each trench (3) via a silicon oxide film (4). The plurality of embedded electrodes (5) include two types of embedded electrodes (5a and 5b) to which voltages are applied separately. By blocking each region between neighboring trenches (3) with a depletion layer (10) formed around every trench (3), current flowing through each region between the neighboring trenches (3) is interrupted. By deleting the depletion layer (10a) formed around the trench (3a) filled with the embedded electrode (5a), current can flow through each region between neighboring trenches (3).

摘要翻译： 提供了其中导通电阻大大降低的半导体器件。 半导体器件包括n型外延层（2），其中相邻沟槽（3）之间的每个区域变为沟道（9），并且多个嵌入电极（5）分别形成在每个沟槽的内表面上 （3）通过氧化硅膜（4）。 多个嵌入电极（5）包括分别施加电压的两种类型的嵌入电极（5a和5b）。 通过用围绕每个沟槽（3）形成的耗尽层（10）阻挡相邻沟槽（3）之间的每个区域，流过在相邻沟槽（3）之间的每个区域的电流被中断。 通过删除形成在填充有嵌入电极（5a）的沟槽（3a）周围的耗尽层（10a），电流可流过相邻沟槽（3）之间的每个区域。

公开(公告)号：US20100176443A1

公开(公告)日：2010-07-15

申请号：US12664841

申请日：2008-06-13

申请人： Masaru Takaishi

发明人： Masaru Takaishi

IPC分类号： H01L29/78 ,  H01L27/06

CPC分类号： H01L29/7808 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/7839 ,  H01L29/866 ,  H01L29/872

摘要： Provided is a semiconductor device in which on-resistance is largely reduced. In a region (2a) of an N type epitaxial layer (2) of the semiconductor device 20, each region between neighboring trenches (3) is blocked with a depletion layer (14) formed around a trench (3) so that a current passage (12) is interrupted, while a part of the depletion layer (14) formed around the trench (3) is deleted so that the current passage (12) is opened. In a region (2b), a junction portion (8) between the N type epitaxial layer (2) and a P+ type diffusion region (7) makes a Zener diode (8).

摘要翻译： 提供了其中导通电阻大大降低的半导体器件。 在半导体器件20的N型外延层（2）的区域（2a）中，相邻沟槽（3）之间的每个区域被形成在沟槽（3）周围的耗尽层（14）阻挡，使得电流通道 （12）中断，而形成在沟槽（3）周围的耗尽层（14）的一部分被删除，使得电流通道（12）打开。 在区域（2b）中，N型外延层（2）与P +型扩散区（7）之间的接合部（8）形成齐纳二极管（8）。

公开(公告)号：US20090302379A1

公开(公告)日：2009-12-10

申请号：US11922092

申请日：2006-06-07

申请人： Masaru Takaishi

发明人： Masaru Takaishi

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766

摘要： A trench semiconductor device is provided which ensures a reduced turn-on time. The semiconductor device (1) includes: a first epitaxial layer provided on a semiconductor substrate; a second epitaxial layer provided in contact with an upper surface of the first epitaxial layer and having a lower impurity concentration than the first epitaxial layer; a plurality of trenches provided in the second epitaxial layer as extending downward from an upper surface of the second epitaxial layer; a gate electrode embedded in each of the trenches; a source region extending downward from the upper surface of the second epitaxial layer along each of opposite side surfaces of the trench; a base region extending downward from a lower surface of the source region along each of the opposite side surfaces of the trench; and a base high concentration region provided adjacent the source region and the base region in spaced relation from the trench as extending downward from the upper surface of the second epitaxial layer to a greater depth than the base region, and having the same conductivity type as the base region and a higher impurity concentration than the base region.

摘要翻译： 提供了一种沟槽半导体器件，其确保了降低的导通时间。 半导体器件（1）包括：设置在半导体衬底上的第一外延层; 第二外延层，设置成与第一外延层的上表面接触并且具有比第一外延层低的杂质浓度; 设置在所述第二外延层中的从所述第二外延层的上表面向下延伸的多个沟槽; 嵌入每个沟槽中的栅电极; 源区域，从所述第二外延层的上表面向下延伸，沿所述沟槽的相对侧表面的每一个; 从所述源极区域的下表面沿所述沟槽的相对侧表面的每一个向下延伸的基极区域; 以及从第二外延层的上表面向下延伸到与基底区域相比更大的深度的与沟槽间隔开的与源极区域和基极区域相邻设置的基极高浓度区域，并具有与基底区域相同的导电类型 碱基区域和比碱性区域更高的杂质浓度。

公开(公告)号：US07598586B2

公开(公告)日：2009-10-06

申请号：US10577361

申请日：2004-12-24

申请人： Masaru Takaishi

发明人： Masaru Takaishi

IPC分类号： H01L29/72

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0873 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66712

摘要： A semiconductor device, including: a semiconductor substrate of a first conductivity; and a semiconductor layer provided on the semiconductor substrate and having a super junction structure including drift layers of the first conductivity and RESURF layers of a second conductivity different from the first conductivity, the drift layers and the RESURF layers being laterally arranged in alternate relation parallel to the semiconductor substrate, the RESURF layers being each provided alongside an interior side wall of a trench penetrating through the semiconductor layer, the drift layers each having an isolation region present between the RESURF layer and the semiconductor substrate to prevent the RESURF layer from contacting the semiconductor substrate.

摘要翻译： 一种半导体器件，包括：第一导电性的半导体衬底; 以及半导体层，其设置在所述半导体衬底上并且具有包含具有不同于所述第一导电性的第二导电性的第一导电性漂移层和RESURF层的超结结构，所述漂移层和所述RESURF层以与 所述半导体衬底，所述RESURF层分别设置在穿过所述半导体层的沟槽的内侧壁旁边，所述漂移层各自具有存在于所述RESURF层和所述半导体衬底之间的隔离区域，以防止所述RESURF层与所述半导体层接触 基质。

公开(公告)号：US20090050961A1

公开(公告)日：2009-02-26

申请号：US11918165

申请日：2006-04-11

申请人： Masaru Takaishi

发明人： Masaru Takaishi

IPC分类号： H01L27/07

CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/42376 ,  H01L29/7395

摘要： A semiconductor device is disclosed which has a shorter turn-on time. The semiconductor device includes an epitaxial layer, two base regions embedded in a surface portion of the epitaxial layer, source regions respectively embedded in the base regions, a drain region including at least a portion of the epitaxial layer excluding the base regions, and a gate electrode provided on the epitaxial layer with the intervention of an insulation film with ends thereof respectively opposed to surfaces of the two base regions. The drain region is arranged so that depletion layers respectively extending from boundaries between the drain region and the two base regions are connected to each other in an OFF state in a portion of the drain region located between the two base regions.

摘要翻译： 公开了一种具有较短开启时间的半导体器件。 半导体器件包括外延层，嵌入在外延层的表面部分中的两个基极区域，分别嵌入基极区域中的源极区域，包括除了基极区域之外的外延层的至少一部分的漏极区域和栅极 电极设置在外延层上，介于绝缘膜之间，其端部分别与两个基极区域的表面相对。 漏极区域被布置成使得分别从漏极区域和两个基极区域之间的边界延伸的耗尽层在位于两个基极区域之间的漏极区域的部分处于断开状态彼此连接。

公开(公告)号：US06798018B2

公开(公告)日：2004-09-28

申请号：US10167490

申请日：2002-06-13

申请人： Masaru Takaishi ,  Koichi Kitaguro ,  Hiroki Takada

发明人： Masaru Takaishi ,  Koichi Kitaguro ,  Hiroki Takada

IPC分类号： H01L2976

CPC分类号： H01L29/7811 ,  H01L21/763 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7808 ,  H01L29/7813

摘要： A semiconductor device has a cell region where transistor cells of a trench structure are arranged in a matrix form, in which a recessed trench is formed in a semiconductor layer, a gate oxide film is formed inside the recessed trench, and a gate electrode formed of polysilicon is disposed inside the recessed trench. To have contact with a gate wiring formed of a metal film, a gate pad disposed continuously to the gate electrode is placed inside a recessed part formed in the same depth as the recessed trench. Consequently, many transistor cells of the trench structure are formed in a matrix form. Even in a semiconductor device where the gate wiring formed of a metal film is contacted with the gate electrode, a semiconductor device of a structure allowing gate voltage to be increased sufficiently can be obtained.

摘要翻译： 半导体器件具有其中沟槽结构的晶体管单元以矩阵形式布置的单元区域，其中在半导体层中形成凹陷沟槽，在凹槽内形成栅极氧化膜，以及栅极电极由 多晶硅设置在凹槽内。 为了与由金属膜形成的栅极布线接触，连续设置到栅电极的栅极焊盘放置在与凹槽相同的深度形成的凹部内部。 因此，沟槽结构的许多晶体管单元以矩阵形式形成。 即使在由金属膜形成的栅极布线与栅电极接触的半导体器件中，也可以获得允许栅极电压充分增加的结构的半导体器件。

公开(公告)号：US08299524B2

公开(公告)日：2012-10-30

申请号：US11195869

申请日：2005-08-03

申请人： Masaru Takaishi

发明人： Masaru Takaishi

IPC分类号： H01L29/78

CPC分类号： H01L29/0634 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor device including a drain region of a first conductivity type formed on a semiconductor substrate; an element forming region that is provided on the drain region and that has a concave portion reaching the drain region; a gate electrode disposed in the concave portion; a superjunction structure portion that is disposed in the element forming region and that is formed by alternately arranging a drift layer of the first conductivity type penetrated by the concave portion and a resurf layer of a second conductivity type being in contact with the drift layer on the semiconductor substrate; and a base region of the second conductivity type that is disposed on the superjunction structure portion so as to be in contact with the drift layer in the element forming region, that is penetrated by the concave portion, and that faces the gate electrode with the gate insulating film therebetween.

摘要翻译： 一种半导体器件，包括形成在半导体衬底上的第一导电类型的漏极区域; 元件形成区域，其设置在漏极区域上并具有到达漏极区域的凹部; 设置在所述凹部中的栅电极; 一个超结构结构部分，其设置在元件形成区域中，并且通过交替地布置由凹部贯穿的第一导电类型的漂移层和与第二导电类型的漂浮层接触的漂浮层而形成的 半导体衬底; 以及第二导电类型的基极区域，其设置在所述超结构部分上，以与所述元件形成区域中的所述漂移层接触，所述漂移层穿过所述凹部，并且所述栅极电极与所述栅极 绝缘膜。