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公开(公告)号：US08692566B2
公开(公告)日：2014-04-08
申请号：US13118585
申请日：2011-05-31
IPC分类号： G01R31/00
CPC分类号： G06F11/2733 , G01R31/2834 , G01R31/31907 , H04L43/50
摘要： Provided is a test apparatus comprising a plurality of testing sections and a synchronizing section that synchronizes operation of at least two testing sections among the plurality of testing sections. Each testing section transmits a synchronization standby command to the synchronizing section when a predetermined condition is fulfilled during execution of the corresponding program and the testing section enters a synchronization standby state, and on a condition that the synchronization standby commands have been received from all of one or more predetermined testing sections among the plurality of testing sections, the synchronizing section supplies a synchronization signal, which ends the synchronization standby state, in synchronization to two or more predetermined testing sections among the plurality of testing sections.
摘要翻译： 提供了一种测试装置，包括多个测试部分和同步部分，其同步多个测试部分中的至少两个测试部分的操作。 当在相应的程序的执行期间满足预定条件并且测试部分进入同步待机状态时，每个测试部分向同步部分发送同步待机命令，并且在从所有一个接收到同步待命命令的条件下， 多个测试部中的多个预定测试部分，同步部分同步地将多个测试部分中的两个或更多个预定测试部分同步地提供结束同步待机状态的同步信号。
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公开(公告)号：US20110288810A1
公开(公告)日：2011-11-24
申请号：US13118470
申请日：2011-05-30
IPC分类号： G06F19/00
CPC分类号： G01R31/31711 , G01R31/2834 , G01R31/318511 , G01R31/31935 , H04L41/069 , H04L43/50
摘要： Provided is a test apparatus that tests a device under test, comprising a testing section that stores a program in which commands to be executed branch according to detected branching conditions and that tests the device under test by executing the program; and a log memory that stores test results of the testing section in association with command paths of the program executed to obtain the test results. The testing section sequentially changes a characteristic of a test signal supplied to the device under test, and judges pass/fail of the device under test for each characteristic of the test signal, and the log memory stores a test result of the testing section in association with a command path of the program, for each characteristic of the test signal.
摘要翻译： 提供了一种测试被测设备的测试装置，包括：测试部，其存储根据检测到的分支条件进行分支的执行命令的程序，并通过执行程序来测试被测设备; 以及日志存储器，其存储与执行的程序的命令路径相关联的测试部分的测试结果以获得测试结果。 测试部分顺序地改变提供给被测设备的测试信号的特性，并且根据测试信号的每个特性判断被测设备的通过/失败，并且日志存储器将测试部分的测试结果相关联 具有程序的命令路径，用于测试信号的每个特性。
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公开(公告)号：US20100142392A1
公开(公告)日：2010-06-10
申请号：US12569796
申请日：2009-09-29
IPC分类号： H04L12/26
CPC分类号： H04L43/50
摘要： There is provided a test apparatus for testing at least one device under test, including a packet list storing section that stores a plurality of packet lists each of which includes a series of packets communicated between the test apparatus and the at least one device under test, a flow control section that designates an order of executing the plurality of packet lists in accordance with an execution flow of a test program that is designed to test the at least one device under test, and a packet communicating section that sequentially communicates the series of packets included in packet lists sequentially designated by the flow control section between the test apparatus and the at least one device under test, to test the at least one device under test.
摘要翻译： 提供了一种用于测试至少一个被测设备的测试装置，包括存储多个分组列表的分组列表存储部分，每个分组列表包括在测试设备和被测试的至少一个设备之间传送的一系列分组， 根据被设计为测试被测试的至少一个设备的测试程序的执行流程来指定执行多个分组列表的顺序的流程控制部分，以及顺序地传送一系列分组的分组通信部分 包括在由测试装置和被测试的至少一个设备之间由流量控制部分顺序指定的分组列表中，以测试被测试的至少一个设备。
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4.发明授权Pattern generating method, pattern generator using the method, and memory tester using the pattern generator 失效图案生成方法，使用该方法的图案生成器，以及使用图案生成器的存储器测试器公开(公告)号：US06601204B1
公开(公告)日：2003-07-29
申请号：US09717715
申请日：2000-11-21
申请人： Masaru Tsuto
发明人： Masaru Tsuto
IPC分类号： G01R3128
摘要： After initializing a Direct Rambus DRAM under test with initialization data, an address, pattern data and mask data are provided to the memory to effect therein a byte-wise masked write of the pattern data, and parallel mask data is converted to plural pieces of serial mask data in accordance with burst addresses generated in a burst address generating means. Based on the bit logical value of each serial mask data, it is decided whether data of each byte is write-enabled or not in the byte-wise masked write, based on the bit logical value of each serial mask data and either one of the initialization data and the byte-wise masked written pattern data is selected to generate expectation data.
摘要翻译： 在初始化用初始化数据测试的直接Rambus DRAM之后，将地址，模式数据和掩模数据提供给存储器，以在其中进行字节屏蔽的模式数据写入，并且并行掩模数据被转换成多个串行 根据在脉冲串地址产生装置中产生的脉冲串地址的掩码数据。 基于每个串行掩码数据的位逻辑值，基于每个串行掩码数据的位逻辑值，确定每个字节的数据是否在字节屏蔽写入中被写使能， 选择初始化数据和字节屏蔽的写入模式数据以产生期望数据。
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公开(公告)号：US08666691B2
公开(公告)日：2014-03-04
申请号：US13118470
申请日：2011-05-30
CPC分类号： G01R31/31711 , G01R31/2834 , G01R31/318511 , G01R31/31935 , H04L41/069 , H04L43/50
摘要： Provided is a test apparatus that tests a device under test, comprising a testing section that stores a program in which commands to be executed branch according to detected branching conditions and that tests the device under test by executing the program; and a log memory that stores test results of the testing section in association with command paths of the program executed to obtain the test results. The testing section sequentially changes a characteristic of a test signal supplied to the device under test, and judges pass/fail of the device under test for each characteristic of the test signal, and the log memory stores a test result of the testing section in association with a command path of the program, for each characteristic of the test signal.
摘要翻译： 提供了一种测试被测设备的测试装置，包括：测试部，其存储根据检测到的分支条件进行分支的执行命令的程序，并通过执行程序来测试被测设备; 以及日志存储器，其存储与执行的程序的命令路径相关联的测试部分的测试结果以获得测试结果。 测试部分顺序地改变提供给被测设备的测试信号的特性，并且根据测试信号的每个特性判断被测设备的通过/失败，并且日志存储器将测试部分的测试结果相关联 具有程序的命令路径，用于测试信号的每个特性。
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公开(公告)号：US20110137606A1
公开(公告)日：2011-06-09
申请号：US12962569
申请日：2010-12-07
IPC分类号： G06F19/00
CPC分类号： H04L43/50 , G01R31/2834
摘要： Provided is a test apparatus that tests a device under test, comprising: a plurality of channels that output and receive signals to and from the device under test; a generating section that generates a packet data sequence transmitted to and from the device under test; and a channel selecting section that selects which of the channels is used to transmit the packet data sequence generated by the generating section.
摘要翻译： 提供了一种测试被测设备的测试设备，包括：向被测设备输出信号和从被测设备接收信号的多个通道; 生成部，其生成从被测设备发送的分组数据序列; 以及频道选择部，选择哪个信道用于发送由生成部生成的分组数据序列。
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公开(公告)号：US20100142393A1
公开(公告)日：2010-06-10
申请号：US12569806
申请日：2009-09-29
IPC分类号： H04L12/26
CPC分类号： H04L49/90 , H04L41/145 , H04L43/50
摘要： There is provided a test apparatus for testing a device under test, including a receiving section that receives a packet from the device under test, a packet data sequence storing section that stores a data sequence included in each type of packet and received data included in the packet received by the receiving section, a transmission data processing section that reads data from the packet data sequence storing section and generates a test data sequence by adjusting a predetermined portion of a data sequence of a packet to be transmitted to the device under test to have a value corresponding to the received data, and a transmitting section that transmits the test data sequence generated by the transmission data processing section to the device under test.
摘要翻译： 提供了一种用于测试被测设备的测试设备，包括接收来自被测设备的分组的接收部分，分组数据序列存储部分，其存储包括在每种类型的分组中的数据序列和接收的数据 由接收部分接收的分组，发送数据处理部分，其从分组数据序列存储部分读取数据，并通过调整要发送到被测设备的数据包的数据序列的预定部分来生成测试数据序列，以具有 与接收到的数据相对应的值，以及发送部，其将由发送数据处理部生成的测试数据序列发送给被测设备。
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8.发明授权Test pattern generator, a testing device, and a method of generating a plurality of test patterns 有权测试模式发生器，测试装置以及产生多个测试模式的方法公开(公告)号：US06769083B1
公开(公告)日：2004-07-27
申请号：US09437249
申请日：1999-11-10
申请人： Masaru Tsuto , Tatsuya Yamada
发明人： Masaru Tsuto , Tatsuya Yamada
IPC分类号： G06F1100
CPC分类号： G01R31/31921
摘要： A test pattern generator for generating a test pattern for testing electrical characteristics of an electrical device. The test pattern generator comprises a pattern memory (32), a pattern cache memory (54, 180 and 182), a vector memory (12), a read out controller (14 and 170), and a transfer controller (34 and 178). The pattern memory (32) stores the test pattern. The pattern cache memory (54, 180 and 182) stores the test pattern read out from the pattern memory (32). The vector memory (12) stores a vector instruction indicating an order of the test pattern to be generated. The read out controller (14 and 170) judges whether an address of the test pattern to be read out from the pattern memory (32) is to be jumped or not based on the vector instruction read out from the vector memory (12). The transfer controller (34 and 178) reads out the test pattern from the jumped address, and for transferring the jumped address to a pattern cache memory (54, 180 and 182) when the read out controller (14 and 170) judges the address is to be jumped.
摘要翻译： 一种用于产生用于测试电气设备的电特性的测试图案的测试图案发生器。 测试图案生成器包括图形存储器（32），图案高速缓冲存储器（54,180和182），向量存储器（12），读出控制器（14和170）以及传送控制器（34和178） 。 图案存储器（32）存储测试图案。 图案高速缓冲存储器（54,180和182）存储从图案存储器（32）读出的测试图案。 矢量存储器（12）存储指示要生成的测试图案的顺序的矢量指令。 读出控制器（14和170）基于从向量存储器（12）读出的向量指令来判断是否要跳过要从模式存储器（32）读出的测试图案的地址。 传输控制器（34和178）从跳转的地址读出测试模式，并且当读出的控制器（14和170）判断地址是，将跳转的地址传送到模式高速缓冲存储器（54,180和182） 要跳了
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公开(公告)号：US06678852B2
公开(公告)日：2004-01-13
申请号：US09865811
申请日：2001-05-23
申请人： Masaru Tsuto
发明人： Masaru Tsuto
IPC分类号： G01R3128
CPC分类号： G01R31/31937 , G01R31/31935
摘要： An address signal, a device control signal and a test pattern data outputted from a pattern generating part are applied to a semiconductor device under test, a response output signal from the semiconductor device under test is compared by a logical comparison part with an expected value data outputted from the pattern generating part, and the logical comparison part generates upon detection of a discordance in the comparison result a failure data representing a failure memory cell, which data is stored together with the address signal, the device control signal and the expected value data outputted from the pattern generating part in a data failure memory, wherein a variable delay part that can give arbitrary time delays to the address signal, the expected value data, and the device control signal, respectively is provided on a data transmission path connecting the pattern generating part to the data failure memory.
摘要翻译： 将从图案生成部输出的地址信号，器件控制信号和测试图案数据施加到被测半导体器件，将来自被测半导体器件的响应输出信号与逻辑比较部与预期值数据进行比较 从所述图案生成部输出，所述逻辑比较部在检测到所述比较结果中的不一致时，生成表示故障存储单元的故障数据，所述故障数据与所述地址信号一起存储，所述设备控制信号和所述期望值数据 在数据故障存储器中从模式产生部分输出，其中分别对地址信号，期望值数据和设备控制信号给出任意时间延迟的可变延迟部分分别设置在连接图形的数据传输路径上 生成部分到数据故障存储器。
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10.发明授权Test pattern generator, a memory testing device, and a method of generating a plurality of test patterns 失效测试模式发生器，存储器测试装置以及产生多个测试模式的方法公开(公告)号：US06484282B1
公开(公告)日：2002-11-19
申请号：US09418758
申请日：1999-10-15
申请人： Masaru Tsuto
发明人： Masaru Tsuto
IPC分类号： G01R3128
CPC分类号： G11C29/36 , G01R31/31813 , G01R31/31921
摘要： A test pattern generator for generating a plurality of test patterns to test a memory comprising: a control memory for storing plural kinds of control instructions to generate the test patterns; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the control memory; a plurality of bank memories for alternately storing vector instructions read out from vector memory and bank memories; an address expander for generating an address of each of control instructions in control memory in accordance with vector instructions stored in a plurality of bank memories; and a test pattern calculator for generating test patterns based on control instructions read out from an address generated by an address expander stored in the control memory.
摘要翻译： 一种测试图形发生器，用于产生用于测试存储器的多个测试图案，包括：控制存储器，用于存储多种控制指令以产生测试图案; 向量存储器，用于存储指示要从控制存储器读出的控制指令的顺序的向量指令; 用于交替地存储从向量存储器和存储体存储器读出的向量指令的多个存储体存储器; 地址扩展器，用于根据存储在多个存储体中的矢量指令来产生控制存储器中每个控制指令的地址; 以及测试图形计算器，用于根据从由存储在控制存储器中的地址扩展器产生的地址中读出的控制指令产生测试模式。
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