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公开(公告)号：US08165027B2
公开(公告)日：2012-04-24
申请号：US12569796
申请日：2009-09-29
IPC分类号： H04J1/16
CPC分类号： H04L43/50
摘要： There is provided a test apparatus for testing at least one device under test, including a packet list storing section that stores a plurality of packet lists each of which includes a series of packets communicated between the test apparatus and the at least one device under test, a flow control section that designates an order of executing the plurality of packet lists in accordance with an execution flow of a test program that is designed to test the at least one device under test, and a packet communicating section that sequentially communicates the series of packets included in packet lists sequentially designated by the flow control section between the test apparatus and the at least one device under test, to test the at least one device under test.
摘要翻译： 提供了一种用于测试至少一个被测设备的测试装置，包括存储多个分组列表的分组列表存储部分，每个分组列表包括在测试设备和被测试的至少一个设备之间传送的一系列分组， 根据被设计为测试被测试的至少一个设备的测试程序的执行流程来指定执行多个分组列表的顺序的流程控制部分，以及顺序地传送一系列分组的分组通信部分 包括在由测试装置和被测试的至少一个设备之间由流量控制部分顺序指定的分组列表中，以测试被测试的至少一个设备。
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公开(公告)号：US08149721B2
公开(公告)日：2012-04-03
申请号：US12569776
申请日：2009-09-29
IPC分类号： H04J1/16
CPC分类号： H04L41/145 , H04L43/50
摘要： There is provided a test apparatus for testing a device under test, including an obtaining section that obtains a packet sequence communicated between the test apparatus and the device under test, from a simulation environment for simulating an operation of the device under test, a packet communication program generating section that generates from the packet sequence a packet communication program for a test, where the packet communication program is to be executed by the test apparatus to communicate packets included in the packet sequence between the test apparatus and the device under test, and a testing section that executes the packet communication program to test the device under test by communicating the packets between the test apparatus and the device under test.
摘要翻译： 提供了一种用于测试被测设备的测试装置，包括：获取部分，用于从用于模拟被测设备的操作的仿真环境中获取在测试设备和被测设备之间传送的分组序列;分组通信 程序生成部，其从所述分组序列生成用于测试的分组通信程序，其中，所述分组通信程序将由所述测试装置执行以将所述分组序列中包括的分组传送到所述测试装置和所述被测试设备之间;以及 测试部分执行分组通信程序以通过在测试设备和被测设备之间传送分组来测试待测设备。
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公开(公告)号：US20110276830A1
公开(公告)日：2011-11-10
申请号：US13035835
申请日：2011-02-25
申请人： Masaru GOISHI , Tokunori AKITA
发明人： Masaru GOISHI , Tokunori AKITA
IPC分类号： G01R31/00
CPC分类号： G01R31/318385 , G01R31/31813 , G01R31/31919
摘要： There is provided a test module comprising a random number generator that generates a pseudo random pattern and includes a controller that generates a register selection signal based on a control instruction stored on an instruction memory, a plurality of polynomial configuration registers one of which is selected by the register selection signal, each polynomial configuration register having polynomial data stored therein, a plurality of initial value configuration registers one of which is selected by the register selection signal, each initial value configuration register having an initial value stored therein, and a random number generation shift register that loads the initial value from the selected one of the plurality of initial value configuration registers and sequentially generates the pseudo random pattern based on the polynomial data stored in the selected one of the plurality of polynomial configuration registers.
摘要翻译： 提供了一种测试模块，包括产生伪随机模式的随机数发生器，并且包括基于存储在指令存储器上的控制指令来生成寄存器选择信号的控制器，多个多项式配置寄存器，其中一个由 寄存器选择信号，存储有多项式数据的各个多项式配置寄存器，其中一个由寄存器选择信号选择的多个初始值配置寄存器，其中存储有初始值的每个初始值配置寄存器和随机数生成 移位寄存器，其从所述多个初始值配置寄存器中的所选择的一个配置寄存器中加载初始值，并且基于存储在所述多个多项式配置寄存器中的所选择的多项式配置寄存器中的多项式数据来顺序地生成所述伪随机模式。
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公开(公告)号：US20080234965A1
公开(公告)日：2008-09-25
申请号：US11690141
申请日：2007-03-23
申请人： MASARU GOISHI
发明人： MASARU GOISHI
IPC分类号： G06F19/00
CPC分类号： G01R31/31937 , G01R31/31922
摘要： A test apparatus for testing a device under test is provided. The test apparatus includes: a timing data output section for outputting timing data to define at least one of a timing of modifying a test signal provided to the device under test and a timing of acquiring an output signal outputted by the device under test; a variable delay circuit for delaying a reference clock pulse of the test apparatus by a delay amount corresponding to designated delay data so as to generate a timing signal having a transition point corresponding to the at least one timing; and a range modification section for modifying the modification amount of the delay data when the timing data are changed by one unit in response to a change of a setting range within which the at least one timing is set.
摘要翻译： 提供了一种用于测试被测设备的测试设备。 测试装置包括：定时数据输出部分，用于输出定时数据，以定义修改提供给被测设备的测试信号的定时和获取被测器件输出的输出信号的定时中的至少一个; 可变延迟电路，用于将测试装置的参考时钟脉冲延迟与指定的延迟数据相对应的延迟量，以产生具有与至少一个定时对应的转变点的定时信号; 以及范围修改部分，用于响应于设定了至少一个定时的设定范围的变化，当定时数据被改变一个单位时，修改延迟数据的修改量。
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公开(公告)号：US08666691B2
公开(公告)日：2014-03-04
申请号：US13118470
申请日：2011-05-30
CPC分类号： G01R31/31711 , G01R31/2834 , G01R31/318511 , G01R31/31935 , H04L41/069 , H04L43/50
摘要： Provided is a test apparatus that tests a device under test, comprising a testing section that stores a program in which commands to be executed branch according to detected branching conditions and that tests the device under test by executing the program; and a log memory that stores test results of the testing section in association with command paths of the program executed to obtain the test results. The testing section sequentially changes a characteristic of a test signal supplied to the device under test, and judges pass/fail of the device under test for each characteristic of the test signal, and the log memory stores a test result of the testing section in association with a command path of the program, for each characteristic of the test signal.
摘要翻译： 提供了一种测试被测设备的测试装置，包括：测试部，其存储根据检测到的分支条件进行分支的执行命令的程序，并通过执行程序来测试被测设备; 以及日志存储器，其存储与执行的程序的命令路径相关联的测试部分的测试结果以获得测试结果。 测试部分顺序地改变提供给被测设备的测试信号的特性，并且根据测试信号的每个特性判断被测设备的通过/失败，并且日志存储器将测试部分的测试结果相关联 具有程序的命令路径，用于测试信号的每个特性。
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公开(公告)号：US20110137606A1
公开(公告)日：2011-06-09
申请号：US12962569
申请日：2010-12-07
IPC分类号： G06F19/00
CPC分类号： H04L43/50 , G01R31/2834
摘要： Provided is a test apparatus that tests a device under test, comprising: a plurality of channels that output and receive signals to and from the device under test; a generating section that generates a packet data sequence transmitted to and from the device under test; and a channel selecting section that selects which of the channels is used to transmit the packet data sequence generated by the generating section.
摘要翻译： 提供了一种测试被测设备的测试设备，包括：向被测设备输出信号和从被测设备接收信号的多个通道; 生成部，其生成从被测设备发送的分组数据序列; 以及频道选择部，选择哪个信道用于发送由生成部生成的分组数据序列。
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公开(公告)号：US20100142393A1
公开(公告)日：2010-06-10
申请号：US12569806
申请日：2009-09-29
IPC分类号： H04L12/26
CPC分类号： H04L49/90 , H04L41/145 , H04L43/50
摘要： There is provided a test apparatus for testing a device under test, including a receiving section that receives a packet from the device under test, a packet data sequence storing section that stores a data sequence included in each type of packet and received data included in the packet received by the receiving section, a transmission data processing section that reads data from the packet data sequence storing section and generates a test data sequence by adjusting a predetermined portion of a data sequence of a packet to be transmitted to the device under test to have a value corresponding to the received data, and a transmitting section that transmits the test data sequence generated by the transmission data processing section to the device under test.
摘要翻译： 提供了一种用于测试被测设备的测试设备，包括接收来自被测设备的分组的接收部分，分组数据序列存储部分，其存储包括在每种类型的分组中的数据序列和接收的数据 由接收部分接收的分组，发送数据处理部分，其从分组数据序列存储部分读取数据，并通过调整要发送到被测设备的数据包的数据序列的预定部分来生成测试数据序列，以具有 与接收到的数据相对应的值，以及发送部，其将由发送数据处理部生成的测试数据序列发送给被测设备。
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公开(公告)号：US20080232538A1
公开(公告)日：2008-09-25
申请号：US11688834
申请日：2007-03-20
申请人： MASARU GOISHI
发明人： MASARU GOISHI
IPC分类号： G01F15/06
CPC分类号： G01R31/31932 , G01R23/10 , G01R31/31922 , G01R31/31928
摘要： Provided is a test apparatus for testing a device under test, the test apparatus including: a pattern generator that generates an expected value pattern of an output signal of the device under test; a timing generator that generates a timing signal indicating a timing for acquiring the output signal of the device under test by delaying a reference clock; a comparator that acquires the output signal of the device under test at the timing designated by the timing signal and compares the acquired output signal to the expected value pattern; and a measurement circuit that starts operating at the timing designated by the timing signal and counts a number of pulses of the output signal of the device under test.
摘要翻译： 提供了一种用于测试被测设备的测试设备，该测试设备包括：产生被测设备的输出信号的期望值模式的模式发生器; 定时发生器，其通过延迟参考时钟产生指示用于获取被测器件的输出信号的定时的定时信号; 比较器，在由定时信号指定的定时获取被测器件的输出信号，并将获取的输出信号与期望值模式进行比较; 以及测量电路，其在由定时信号指定的定时开始运行，并对被测器件的输出信号的脉冲数进行计数。
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公开(公告)号：US07363566B2
公开(公告)日：2008-04-22
申请号：US11136075
申请日：2005-05-24
申请人： Masaru Goishi
发明人： Masaru Goishi
IPC分类号： G06F11/00
CPC分类号： G01R31/31813 , G11C29/48 , G11C29/56 , G11C29/56004 , G11C2029/5602 , G11C2029/5606
摘要： There is provided a pattern generator that generates a test pattern for testing an electronic device using test data previously supplied. The pattern generator includes a cache memory, a main memory operable to store a plurality of test data blocks of which each block is the test data of the magnitude capable of being stored on the cache memory, and an instruction memory operable to store instruction information showing sequence in which the plurality of test data blocks should be stored on the cache memory, in which the pattern generator sequentially outputs the test data blocks stored on the cache memory as the test pattern. It is preferable that the instruction memory stores the instruction information showing all sequence of the test data blocks to be stored on the cache memory in order to generate the test pattern before beginning to generate the test pattern.
摘要翻译： 提供了一种模式生成器，其生成使用先前提供的测试数据来测试电子设备的测试模式。 图案生成器包括高速缓冲存储器，主存储器，其可操作以存储多个测试数据块，每个测试数据块的每个块是能够存储在高速缓冲存储器上的幅度的测试数据;以及指令存储器，其可操作以存储显示 其中多个测试数据块应存储在高速缓冲存储器上的顺序，其中模式发生器顺序地输出存储在高速缓存存储器上的测试数据块作为测试模式。 优选地，指令存储器存储表示要存储在高速缓存存储器上的所有测试数据块序列的指令信息，以便在开始生成测试模式之前生成测试模式。
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公开(公告)号：US07336714B2
公开(公告)日：2008-02-26
申请号：US10850048
申请日：2004-05-20
申请人： Masaru Goishi
发明人： Masaru Goishi
IPC分类号： H03H7/30
CPC分类号： G01R31/31922 , H03K5/135 , H04L7/0037 , H04L7/0041 , H04L7/0331
摘要： A phase adjustment apparatus and a semiconductor test apparatus for automatically correcting irregularities of propagation delay of a transmission signal, so that the transmission signal transmitted between apparatuses while synchronized with a high-speed clock can be received at a stable optimal timing at a receiving end. The phase adjustment apparatus for transmitting a transmission signal synchronized with a clock between a first apparatus of the sending end and a second apparatus of the receiving end includes phase adjustment means used when retiming the transmission signal with the clock of the receiving end of the second apparatus. That is, the phase adjustment means corrects an unknown phase relationship between the clock of the receiving end and the transmission signal and delays the transmission signal by a specified amount for adjustment so that the signal can be received with a stable retiming condition.
摘要翻译： 一种用于自动校正发送信号的传播延迟的不规则性的相位调整装置和半导体测试装置，从而可以在接收端的稳定的最佳定时接收与高速时钟同步的装置之间发送的发送信号。 用于发送与发送端的第一装置和接收端的第二装置之间的时钟同步的发送信号的相位调整装置包括当用第二装置的接收端的时钟重新定时发送信号时使用的相位调整装置 。 也就是说，相位调整装置校正接收端的时钟与发送信号之间的未知相位关系，并且将发送信号延迟指定量以进行调整，使得可以以稳定的重新定时状态接收信号。
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