摘要:
For patterning an opening through a patterned material, a coating material, a slow-etch material, and a photoresist material are deposited over the patterned material. The opening is patterned through the photoresist material, and the slow-etch material exposed through the opening is etched away. The photoresist material and the coating material exposed through the opening are then etched away. A remaining portion of the slow-etch hard-mask material and the patterned material exposed through the opening are then etched away such that the coating material outside of the opening is exposed. A remaining portion of the coating material is then etched away with an etch agent that does not etch the patterned material.
摘要:
Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.
摘要:
Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.
摘要:
With standard DUV lithography technology it is not easy to achieve MOS transistor gates in sub-100 nm range. With the method of trim-etching in HI/O2 plasmas there is an opportunity to use the current lithography tools, to reduce the dimensions of the resist feature, and to achieve sub-100 nm MOS transistor gates for advanced devices. The method of trim-etching in HI/O2 plasmas delivers another factor to control the critical dimension of the MOS devices very accurately. Therefore, this invention helps to significantly reduce the total cost for manufacturing small MOS devices with a critical dimension in the sub-100 nm range.