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    Self-aligned gate realignment employing planarizing overetch
    4.
    发明授权
    Self-aligned gate realignment employing planarizing overetch 失效
    采用平面化过程的自对准栅极重新对准

    公开(公告)号：US4965218A

    公开(公告)日：1990-10-23

    申请号：US235393

    申请日：1988-08-23

    申请人： Arthur E. Geissberger ,  Robert A. Sadler ,  Paulette Luper ,  Matthew L. Balzan

    发明人： Arthur E. Geissberger ,  Robert A. Sadler ,  Paulette Luper ,  Matthew L. Balzan

    IPC分类号： H01L21/285 ,  H01L21/306 ,  H01L21/338 ,  H01L21/768 ,  H01L21/8252 ,  H01L29/10 ,  H01L29/423 ,  H01L29/47 ,  H01L29/812

    CPC分类号： H01L29/812 ,  H01L21/02063 ,  H01L21/28581 ,  H01L21/28587 ,  H01L21/768 ,  H01L21/8252 ,  H01L29/1029 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66878

    摘要： A method of providing a self-aligned gate (SAG) transistor or FET is disclosed. The method permits large aligment tolerances during manufacture of the SAG FET. A reduction in gate resistance is accomplished by including a second layer of gate metallization, which is highly conductive, after the n+ implant and activation anneal without any critical realignment to the first layer of gate metal. The provision of the second layer after the anneal precludes degradation of the conductivity of the second gate metal by interdiffusion with the first (refractory) gate metal during the anneal. The large tolerance for misalignment of the gate mask level is obtained by a planarization of the anneal cap until the top surface of the first layer of gate metal is exposed, all without the need for a separate mask and etch step to open contact "windows" through the planarization anneal cap layers. The remaining adjacent encapsulant then acts as an insulator over the FET channel region and allows for gross misalignment of the second gate metallization without FET performance degradation. Using this technique, substantially increased performance can be obtained from a self-aligned FET while maintaining the basic simplicity of the RG process.

    摘要翻译： 公开了一种提供自对准栅极（SAG）晶体管或FET的方法。 该方法在SAG FET的制造过程中允许大的分配公差。 栅极电阻的降低通过在n +注入和激活退火之后包括第二层栅极金属化（其是高导电性的）而实现，而不对第一栅极金属层进行任何临界重新对准。 在退火之后提供第二层排除了通过在退火期间与第一（难熔）栅极金属的相互扩散来降低第二栅极金属的导电性。 通过退火帽的平坦化，直到栅极金属的第一层的顶表面露出来获得对栅极掩模级别的未对准的大的公差，全部不需要单独的掩模和蚀刻步骤来打开接触“窗口” 通过平坦化退火盖层。 剩余的相邻密封剂随后用作FET沟道区域上的绝缘体，并且允许第二栅极金属化的总体偏移，而不会导致FET性能下降。 使用这种技术，可以在保持RG工艺的基本简单性的同时，从自对准FET获得显着提高的性能。

    Sagfet with buffer layers
    5.
    发明授权
    Sagfet with buffer layers 失效
    Sagfet与缓冲层

    公开(公告)号：US4918493A

    公开(公告)日：1990-04-17

    申请号：US230625

    申请日：1988-08-10

    申请人： Arthur E. Geissberger ,  Robert A. Sadler ,  Gregory E. Menk ,  Matthew L. Balzan

    发明人： Arthur E. Geissberger ,  Robert A. Sadler ,  Gregory E. Menk ,  Matthew L. Balzan

    IPC分类号： H01L29/10

    CPC分类号： H01L29/1075

    摘要： A composite buffer layer is formed with a layer of GaAs on a semi-insulating GaAs substrate. Next a short period superlattice is formed followed by another GaAs layer. A layer of GaAlAs is then provided such that the Ai content and no doping followed by an intrinsic GaAs layer. The intrinsic GaAs layer is the active layer which serves as a channel.

    摘要翻译： 复合缓冲层在半绝缘GaAs衬底上形成有GaAs层。 接下来是形成一个短时间的超晶格，随后是另一个GaAs层。 然后提供一层GaAlAs，使得Ai含量和不含有本征GaAs层的掺杂。 本征GaAs层是用作沟道的有源层。

    Self-aligned gate FET process using undercut etch mask
    8.
    发明授权
    Self-aligned gate FET process using undercut etch mask 失效
    使用底切蚀刻掩模的自对准栅极FET工艺

    公开(公告)号：US4847212A

    公开(公告)日：1989-07-11

    申请号：US137309

    申请日：1987-12-23

    申请人： Matthew L. Balzan ,  Arthur E. Geissberger ,  Robert A. Sadler

    发明人： Matthew L. Balzan ,  Arthur E. Geissberger ,  Robert A. Sadler

    IPC分类号： H01L29/812 ,  H01L21/265 ,  H01L21/285 ,  H01L21/338 ,  H01L21/8252 ,  H01L29/417 ,  H01L29/47

    CPC分类号： H01L29/66878 ,  H01L21/28581 ,  H01L21/28587 ,  H01L21/8252 ,  H01L29/475 ,  H01L29/66848 ,  Y10S148/105 ,  Y10S148/131 ,  Y10S148/143

    摘要： The provision of an intermediately doped transition region between respective n+ implanted source and drain regions in a GaAs FET and the lightly doped channel region under the gate permits device optimizaiton for low source and drain resistance in EFET's while employing the same n+ implant for source and drain optimization in DFET's while also maintaining the same n+ to gate contact spacing in both device types. Additionally, in high frequency operation of an asymmetrically implanted FET, the tapered doping profile offered by the transition region on the drain side of the gate provides high transconductance without sacrificing high output resistance. The transition region can be provided in a self-aligned implant employing dielectric sidewall spacers and the n+ implant can be self-aligned with an etch mask employed in gate definition.

    摘要翻译： 在GaAs FET中的相应n +注入源极和漏极区域之间提供中间掺杂的过渡区域以及栅极下的轻掺杂沟道区域允许器件优化EFET中的低源极和漏极电阻，同时使用相同的n +注入源和漏极 在DFET中进行优化，同时在两种器件类型中也保持相同的n +与栅极接触间距。 另外，在非对称注入的FET的高频工作中，栅极漏极侧的过渡区提供的锥形掺杂分布提供了高的跨导而不牺牲高输出电阻。 可以使用电介质侧壁间隔物在自对准植入物中提供过渡区域，并且n +注入可以与栅极定义中采用的蚀刻掩模自对准。