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公开(公告)号：US09472633B1
公开(公告)日：2016-10-18
申请号：US13305657
申请日：2011-11-28
申请人： Michael Schuette , Andrew Ketterson
发明人： Michael Schuette , Andrew Ketterson
IPC分类号： H01L29/423 , H01L29/66
CPC分类号： H01L29/42316 , H01L23/315 , H01L29/2003 , H01L29/401 , H01L29/66462 , H01L29/7786
摘要： Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a gate, a source pad and a drain pad arranged such that the gate is separated from the source pad and the drain pad by air, and an insulating layer coupled with a portion of the gate such that at least a portion of the insulating layer is separated from the source pad and the drain pad by the air. Methods for making the same also are described.
摘要翻译： 实施例包括但不限于包括微电子器件的设备和系统，该微电子器件包括栅极，源极焊盘和漏极焊盘，其布置成使得栅极与空穴源与源极焊盘和漏极焊盘分离，并且绝缘层与 使得绝缘层的至少一部分通过空气与源极焊盘和漏极焊盘分离。 也对其制作方法进行了说明。
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2.发明授权Raid storage systems having arrays of solid-state drives and methods of operation 有权具有固态驱动器阵列和操作方法的RAID存储系统公开(公告)号：US08898381B2
公开(公告)日：2014-11-25
申请号：US12960626
申请日：2010-12-06
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/0647 , G06F3/0689 , G06F11/1008 , G06F11/108
摘要： RAID storage systems and methods adapted to enable the use of NAND flash-based solid-state drives. The RAID storage system includes an array of solid-state drives and a controller operating to combine the solid-state drives into a logical unit. The controller utilizes data striping to form data stripe sets comprising data (stripe) blocks that are written to individual drives of the array, utilizes distributed parity to write parity data of the data stripe sets to individual drives of the array, and writes the data blocks and the parity data to different individual drives of the array. The RAID storage system detects the number of data blocks of at least one of the data stripe sets and then, depending on the number of data blocks detected, may invert bit values of the parity data or add a dummy data value of “1” to the parity value.
摘要翻译： 适用于使用基于NAND闪存的固态硬盘的RAID存储系统和方法。 RAID存储系统包括固态驱动器阵列和操作以将固态驱动器组合成逻辑单元的控制器。 控制器利用数据条带化形成数据条带集，其中包括写入阵列的各个驱动器的数据（条带）块，利用分布式奇偶校验将数据条带集的奇偶校验数据写入阵列的各个驱动器，并写入数据块 并将奇偶校验数据分配给阵列的不同单独驱动器。 RAID存储系统检测数据条带组中的至少一个的数据块的数量，然后根据检测到的数据块的数量，可以反转奇偶校验数据的位值或将伪数据值“1”添加到 奇偶校验值。
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3.发明授权Mass storage system and method of using hard disk, solid-state media, PCIe edge connector, and raid controller 有权大容量存储系统和使用硬盘，固态介质，PCIe边缘连接器和RAID控制器的方法公开(公告)号：US08725946B2
公开(公告)日：2014-05-13
申请号：US13211760
申请日：2011-08-17
IPC分类号： G06F12/00
CPC分类号： G06F3/0658 , G06F3/0611 , G06F3/0626 , G06F3/0647 , G06F3/0685 , G06F11/1441 , G06F11/2015 , G06F12/0866 , G06F2212/217 , G11B33/128
摘要： Methods and systems for mass storage of data over two or more tiers of mass storage media that include nonvolatile solid-state memory devices, hard disk devices, and optionally volatile memory devices or nonvolatile MRAM in an SDRAM configuration. The mass storage media interface with a host through one or more PCIe lanes on a single printed circuit board.
摘要翻译： 大容量存储包括非易失性固态存储设备，硬盘设备和可选易失性存储设备的两层或多层海量存储介质中的数据的大容量存储方法和系统，或者SDRAM配置中的非易失性MRAM。 大容量存储介质通过单个印刷电路板上的一个或多个PCIe通道与主机进行接口。
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4.发明授权Non-volatile memory-based mass storage devices and methods for writing data thereto 有权基于非易失性存储器的大容量存储设备和用于向其写入数据的方法公开(公告)号：US08694754B2
公开(公告)日：2014-04-08
申请号：US13251491
申请日：2011-10-03
CPC分类号： G06F3/0679 , G06F3/0616 , G06F3/0619 , G06F3/0629 , G06F3/064 , G06F3/0688 , G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7204 , G11C16/349
摘要： A non-volatile solid state memory-based mass storage device having at least one non-volatile memory component and methods of operating the storage device. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.
摘要翻译： 一种具有至少一个非易失性存储器组件的非易失性固态存储器大容量存储设备和操作该存储设备的方法。 在本发明的一个方面，一个或多个存储器组件基于存储在块信息记录中的P / E周期计数来定义划分成用户存储器和过度供应池的存储器空间。 存储设备将擦除块的P / E周期计数传送到主机，并且主机将P / E周期计数存储在内容可寻址存储器中。 在主机向存储设备写入期间，主机发出低的P / E周期计数作为主地址到内容可寻址存储器，该内存可寻址存储器返回过配置池内的块的可用块地址作为多维度中的第一维度 地址空间。 更改的文件优选以附加模式更新，并且可以维护先前版本以进行版本控制。
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公开(公告)号：US20130202452A1
公开(公告)日：2013-08-08
申请号：US13638016
申请日：2011-03-03
IPC分类号： F04D13/04
CPC分类号： F04D13/046 , F01P7/044
摘要： A hydraulic fan drive includes a hydraulic pump that has an adjustable swept volume. The hydraulic pump is assigned a pressure control valve arrangement that is configured to regulate a pump pressure by adjustment of the swept volume. The drive further includes a hydraulic motor configured to drive an impeller wheel and a pressure line, which is connected to a pressure input of the hydraulic motor and into which pressure medium is configured to be conveyed by the hydraulic pump. A hydraulic accumulator is connected to the pressure line and the displacement of the hydraulic motor is configured to be adjusted. Energy is buffer-stored by the hydraulic accumulator by feeding in pressure medium beyond the amount that is displaced by the hydraulic motor. This stored energy becomes free for other operations of a machine, for example, to which the drive is attached.
摘要翻译： 液压风扇驱动器包括具有可调节的扫掠体积的液压泵。 液压泵被分配有压力控制阀装置，其配置成通过调节扫掠体积来调节泵的压力。 驱动装置还包括液压马达，该液压马达构造成驱动叶轮和压力线，该叶轮和压力线连接到液压马达的压力输入端，压力介质构造成由液压泵输送。 液压蓄能器与压力线连接，液压马达的排量被调整。 通过在压力介质中进给超过液压马达所移动量的液体蓄能器来缓冲储存能量。 这种存储的能量对于机器的其他操作变得免费，例如，驱动器附接到机器。
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6.发明申请公开(公告)号：US20130024735A1
公开(公告)日：2013-01-24
申请号：US13185689
申请日：2011-07-19
CPC分类号： G06F11/1415 , G06F11/1048 , G06F11/2084
摘要： Non-volatile solid-state memory-based storage devices and methods of operating the storage devices to have low initial error rates. The storage devices and methods use bit error rate comparison of duplicate writes to one or more non-volatile memory devices. The data set with a lower bit error rate as determined during verification is maintained, whereas data sets with higher bit error rates are discarded. A threshold of bit error rates can be used to trigger the duplication of data for bit error comparison.
摘要翻译： 基于非易失性固态存储器的存储设备和操作存储设备以具有低初始错误率的方法。 存储设备和方法使用对一个或多个非易失性存储器件的重复写入的误码率比较。 保持在验证期间确定的具有较低误码率的数据集，而丢弃具有较高误码率的数据集。 可以使用误码率的阈值来触发用于位错误比较的数据的复制。
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公开(公告)号：US08331123B2
公开(公告)日：2012-12-11
申请号：US12886771
申请日：2010-09-21
IPC分类号： G11C5/06
CPC分类号： G06F3/0658 , G06F3/0611 , G06F3/0688
摘要： A nonvolatile storage device adapted for use with computers, workstations and other processing apparatuses. The storage device includes a printed circuit board, a nonvolatile memory array comprising at least two sub-arrays that contain nonvolatile solid-state memory devices, and control circuitry for interfacing with the processing apparatus. The control circuitry includes an abstraction layer and at least two memory control units configured to communicate data, address and control signals with the sub-arrays of the memory devices. A bus connects each memory control unit to a corresponding one of the sub-arrays. The control circuitry further includes a crossbar switch that functionally connects each memory control unit to the abstraction layer. The storage device is capable of overcoming limitations of current SSD designs by enabling independent read and write transfers (accesses) to the memory devices of the storage device, including concurrent read and write accesses.
摘要翻译： 适用于计算机，工作站和其他处理装置的非易失性存储装置。 存储装置包括印刷电路板，包括至少两个包含非易失性固态存储器件的子阵列的非易失性存储器阵列，以及用于与处理装置接口的控制电路。 控制电路包括抽象层和至少两个存储器控制单元，其被配置为与存储器件的子阵列通信数据，地址和控制信号。 总线将每个存储器控制单元连接到相应的一个子阵列。 所述控制电路还包括功能性地将每个存储器控制单元连接到所述抽象层的交叉开关。 存储设备能够通过对存储设备的存储设备进行独立的读和写传输（访问）来克服当前SSD设计的限制，包括并发读取和写入访问。
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公开(公告)号：US20120144096A1
公开(公告)日：2012-06-07
申请号：US13311723
申请日：2011-12-06
IPC分类号： G06F12/00
CPC分类号： G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/0688 , G06F13/40
摘要： A mass storage system comprising multiple memory cards, each with non-volatile memory components, a system bus interface for communicating with a system bus of a host system, and at least one ancillary interface. The ancillary interface is configured for direct communication of commands, addresses and data between the memory cards via a cross-link connector without accessing the system bus interface.
摘要翻译： 一种大容量存储系统，包括多个存储卡，每个具有非易失性存储器组件，用于与主机系统的系统总线通信的系统总线接口以及至少一个辅助接口。 辅助接口被配置为通过交叉连接器直接通信存储卡之间的命令，地址和数据，而不需要访问系统总线接口。
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9.发明申请METHOD AND APPARATUS FOR USING BIOPOTENTIALS FOR SIMULTANEOUS MULTIPLE CONTROL FUNCTIONS IN COMPUTER SYSTEMS 失效在计算机系统中同时使用多重控制功能的方法和装置公开(公告)号：US20110301488A1
公开(公告)日：2011-12-08
申请号：US12957585
申请日：2010-12-01
CPC分类号： G06F3/015 , A61B5/0488 , G06F3/038 , G06F3/04847
摘要： A biosignal-computer-interface apparatus and method. The apparatus includes one or more devices for generating biosignals based on at least one physiological parameter of an individual, and a computer-interface device capable of performing multiple tasks, including converting the biosignals into at least one input signal, establishing a scale encompassing different levels of the input signal, multiplying the input signal into parallel control channels, dividing the scale into multiple zones for each of the parallel control channels, assigning computer commands to each individual zone of the multiple zones, and generating the computer command assigned to at least one of the individual zones if the level of the input signal is within the at least one individual zone. The individual zones can be the same or different among the parallel control channels.
摘要翻译： 一种生物信号计算机接口设备和方法。 该装置包括用于基于个体的至少一个生理参数产生生物信号的一个或多个装置，以及能够执行多个任务的计算机接口装置，包括将生物信号转换成至少一个输入信号，建立包含不同等级的标度 的输入信号，将输入信号乘以并行控制通道，将标尺分成用于每个并行控制通道的多个区域，将计算机命令分配给多个区域的每个单独的区域，以及生成分配给至少一个 如果输入信号的电平在至少一个单独的区域内。 各个区域在并行控制通道中可以相同或不同。
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公开(公告)号：US20110255337A1
公开(公告)日：2011-10-20
申请号：US13088450
申请日：2011-04-18
IPC分类号： G11C16/10
CPC分类号： G11C16/14 , G11C16/0483
摘要： A NAND flash memory device and method of erasing memory cells thereof, wherein each cell is only subjected to the level of erase voltage needed to restore its nominal “erased” state. Each memory cell of the NAND flash memory device comprises a floating gate, a control gate connected to a wordline and receives a control voltage therefrom to induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge. Each memory cell further includes circuitry for modulating the erase voltage according to the level of the programming charge on its floating gate.
摘要翻译： 一种NAND闪速存储器件和擦除其存储单元的方法，其中每个单元仅经历恢复其标称“擦除”状态所需的擦除电压电平。 NAND闪速存储器件的每个存储器单元包括浮置栅极，连接到字线的控制栅极并从其接收控制电压以在浮置栅极上引起编程电荷，以及适于施加擦除电压以消耗浮置的位线 门的编程费。 每个存储单元还包括用于根据其浮动栅极上的编程电荷的电平来调制擦除电压的电路。
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