公开(公告)号：US07138317B2

公开(公告)日：2006-11-21

申请号：US10831874

申请日：2004-04-26

申请人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

发明人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

IPC分类号： H01L21/8234

CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  Y10S438/981

摘要： A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

摘要翻译： 在由衬底上的STI隔离区隔开的有源区上形成多个栅极氧化物厚度的方法。 将第一层氧化物生长至约50埃的厚度，然后除去选定的区域。 生长比第一生长氧化物薄的第二层氧化物。 对于三种不同的栅极氧化物厚度，选择的第二氧化物生长区域用N 2 O 3等离子体氮化，这增加了栅极氧化物的介电常数并降低了有效的氧化物厚度。 为了实现四种不同的栅极氧化物厚度，对所选择的第一生长氧化物和选择的第二生长氧化物区域进行氮化。 栅极氧化物的氮化还防止杂质掺杂剂跨过栅极氧化物层迁移并减少待机电流的泄漏。 该方法还减少由HF蚀刻剂引起的STI区域的拐角损失。

公开(公告)号：US06759302B1

公开(公告)日：2004-07-06

申请号：US10209433

申请日：2002-07-30

申请人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

发明人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

IPC分类号： H01L31119

CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  Y10S438/981

摘要： A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

公开(公告)号：US07118974B2

公开(公告)日：2006-10-10

申请号：US10831871

申请日：2004-04-26

申请人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

发明人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

IPC分类号： H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  Y10S438/981

摘要： A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

公开(公告)号：US06767847B1

公开(公告)日：2004-07-27

申请号：US10187704

申请日：2002-07-02

申请人： Chien-Ming Hu ,  Chien-Hao Chen ,  Mo-Chiun Yu ,  Shih-Chang Chen ,  Mong-Song Liang

发明人： Chien-Ming Hu ,  Chien-Hao Chen ,  Mo-Chiun Yu ,  Shih-Chang Chen ,  Mong-Song Liang

IPC分类号： H01L21324

CPC分类号： H01L21/28185 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/2686 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

摘要： A method of forming a silicon nitride-silicon dioxide composite insulator layer for use as a gate insulator stack for an MOSFET device, has been developed. The method features formation of the silicon dioxide component of the gate insulator stack, after formation of the overlying silicon nitride component, allowing the gate insulator stack to be comprised with a nitrogen profile presenting enhanced barrier characteristic and less interface charge than counterpart silicon nitride-silicon dioxide composites formed wherein the silicon nitride component was deposited on an already grown underlying silicon dioxide layer. Oxygen ions, or oxygen radicals obtained via ultra-violet procedures, penetrate the silicon nitride component and locate in a top portion of the semiconductor substrate. Subsequent annealing allows reaction of the oxygen ions or radicals with a top portion of the semiconductor substrate resulting in the desired silicon dioxide component underlying silicon nitride.

摘要翻译： 已经开发了形成用作MOSFET器件的栅极绝缘体堆叠的氮化硅 - 二氧化硅复合绝缘体层的方法。 该方法在形成上覆氮化硅组分之后形成栅极绝缘体叠层的二氧化硅组分，允许栅极绝缘体堆叠包含具有增强的势垒特性和较少的对应氮化硅 - 硅的界面电荷的氮分布 形成二氧化硅复合物，其中氮化硅组分沉积在已经生长的下层二氧化硅层上。 通过紫外线工艺获得的氧离子或氧自由基穿透氮化硅组分并位于半导体衬底的顶部。 随后的退火允许氧离子或自由基与半导体衬底的顶部部分反应，导致氮化硅下面所需的二氧化硅组分。

公开(公告)号：US06566205B1

公开(公告)日：2003-05-20

申请号：US10043481

申请日：2002-01-11

申请人： Mo-Chiun Yu ,  Chien-Hao Chen

发明人： Mo-Chiun Yu ,  Chien-Hao Chen

IPC分类号： H01L21336

CPC分类号： H01L21/28202 ,  H01L21/3003 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

摘要： To achieve a lower operating gate voltage for an FET, while avoiding breakdown and similar problems, a high K dielectric such as aluminum or zirconium oxide can be used As deposited, these materials tend to have a high density of trapped charge. The present invention discloses how such charge may be neutralized by impregnating the high K dielectric layer with between about 5 and 10 atomic percent of nitrogen. Several methods for introducing the nitrogen are described. These include diffusion from an overlay of silicon nitride, diffusion from a gas source, remote plasma nitridation, and decoupled plasma nitridation.

摘要翻译： 为了实现FET的较低的操作栅极电压，同时避免击穿和类似的问题，可以使用诸如铝或氧化锆的高K电介质。作为沉积，这些材料倾向于具有高密度的俘获电荷。 本发明公开了如何通过用大约5至10原子％的氮浸渍高K介电层来中和这种电荷。 描述了几种用于引入氮的方法。 这些包括来自氮化硅覆盖物的扩散，来自气体源的扩散，远程等离子体氮化和解耦等离子体氮化。

公开(公告)号：US07316970B2

公开(公告)日：2008-01-08

申请号：US10892014

申请日：2004-07-14

申请人： Chien-Hao Chen ,  Ju-Wang Hsu ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Ju-Wang Hsu ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/425

CPC分类号： H01L21/31111 ,  H01L21/823481 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78

摘要： A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for partially covering the original nitride layer. A wet etching is performed to remove the original nitride layer uncovered by the photoresist mask in such a way without causing substantial damage to the isolation structure. As such, the original nitride layer covered by the photoresist mask constitutes the resist protect layer.

摘要翻译： 在半导体衬底上形成抗蚀剂保护层的方法包括以下步骤。 在半导体衬底上形成隔离结构。 在半导体衬底上形成对隔离结构具有实质蚀刻选择性的原始氮化物层。 形成光致抗蚀剂掩模以部分覆盖原始氮化物层。 执行湿蚀刻以以这样的方式去除由光致抗蚀剂掩模未覆盖的原始氮化物层，而不会对隔离结构造成实质损坏。 因此，由光致抗蚀剂掩模覆盖的原始氮化物层构成抗蚀剂保护层。

公开(公告)号：US20060049470A1

公开(公告)日：2006-03-09

申请号：US10936271

申请日：2004-09-07

申请人： Chia-Lin Chen ,  Ming-Jie Huang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chia-Lin Chen ,  Ming-Jie Huang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/76

CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L29/665

摘要： A method for forming a microelectronic product and the microelectronic product resulting from the method both employ a bilayer gate electrode. The bilayer gate electrode employs: (1) a first layer formed of a random oriented polycrystalline silicon material; and (2) a second layer laminated to the first layer and formed of a columnar oriented polycrystalline silicon material. The gate electrode provides enhanced performance to a semiconductor device within which it is formed.

摘要翻译： 形成微电子产物的方法和由该方法得到的微电子产物都采用双层栅电极。 双层栅极采用：（1）由随机取向的多晶硅材料形成的第一层; 和（2）层压到第一层并由柱状取向的多晶硅材料形成的第二层。 栅电极为其形成的半导体器件提供增强的性能。

公开(公告)号：US20050242376A1

公开(公告)日：2005-11-03

申请号：US10834474

申请日：2004-04-29

申请人： Chien-Hao Chen ,  Chia-Lin Chen ,  Tze Lee ,  Shih-Chang Chen ,  Ju-Wang Hsu

发明人： Chien-Hao Chen ,  Chia-Lin Chen ,  Tze Lee ,  Shih-Chang Chen ,  Ju-Wang Hsu

IPC分类号： H01L21/336 ,  H01L21/338 ,  H01L21/76 ,  H01L29/745 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

摘要： A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant.

摘要翻译： 半导体器件包括衬底，设置在衬底上的栅极和形成在栅极两侧的衬底中的源极和漏极。 该器件还包括具有形成在栅极的侧壁上的第一层和第二层的薄间隔物，其中使用相同的蚀刻剂，第一层和第二层具有至少每分钟至少10埃的湿法蚀刻速率。

公开(公告)号：US20080157266A1

公开(公告)日：2008-07-03

申请号：US12049452

申请日：2008-03-17

申请人： Chien-Hao Chen ,  Vincent S. Chang ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Vincent S. Chang ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/762

CPC分类号： H01L21/76235

摘要： A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of the trench surfaces using a nitrogen-containing gas prior to formation of the liner oxide layer, post-formation nitridation of the liner oxide layer, or both pre-treatment of the trench surfaces and post-formation nitridation of the liner oxide layer. The liner modification method of the present invention optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of STI structures and prevents diffusion of dopant into the liner oxide layer during subsequent processing.

摘要翻译： 公开了一种用于STI沟槽中的衬垫氧化物层的新的改进的衬垫修改方法。 根据该方法，在衬底中蚀刻STI沟槽，并且通过氧化技术在沟槽表面上形成衬垫氧化物层。 该方法还包括在形成衬垫氧化物层之前使用含氮气体预处理沟槽表面，衬里氧化物层的形成后氮化或沟槽表面的预处理和后形成氮化 的衬里氧化物层。 本发明的衬垫修改方法优化STI结构的反窄窄度效应（INWE）和栅极氧化物完整性（GOI），并防止掺杂剂在随后的处理期间扩散到衬里氧化物层中。

公开(公告)号：US20060183279A1

公开(公告)日：2006-08-17

申请号：US11279016

申请日：2006-04-07

申请人： Chien-Hao Chen ,  Chia-Lin Chen ,  Ju-Wang Hsu ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Chia-Lin Chen ,  Ju-Wang Hsu ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.

摘要翻译： 一种具有改善的电荷迁移率的应变通道MOSFET器件及其形成方法，所述方法包括在衬底上提供具有半导体导电类型的第一半导体导电类型的第一栅极和第二栅极; 在所述第一栅极上形成具有第一类型应力的第一应变层; 并且在所述第二浇口上形成具有第二类型应力的第二应变层。