公开(公告)号：US06759302B1

公开(公告)日：2004-07-06

申请号：US10209433

申请日：2002-07-30

申请人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

发明人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

IPC分类号： H01L31119

CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  Y10S438/981

摘要： A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

公开(公告)号：US07118974B2

公开(公告)日：2006-10-10

申请号：US10831871

申请日：2004-04-26

申请人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

发明人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

IPC分类号： H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  Y10S438/981

摘要： A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

公开(公告)号：US07138317B2

公开(公告)日：2006-11-21

申请号：US10831874

申请日：2004-04-26

申请人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

发明人： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

IPC分类号： H01L21/8234

CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  Y10S438/981

摘要： A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

摘要翻译： 在由衬底上的STI隔离区隔开的有源区上形成多个栅极氧化物厚度的方法。 将第一层氧化物生长至约50埃的厚度，然后除去选定的区域。 生长比第一生长氧化物薄的第二层氧化物。 对于三种不同的栅极氧化物厚度，选择的第二氧化物生长区域用N 2 O 3等离子体氮化，这增加了栅极氧化物的介电常数并降低了有效的氧化物厚度。 为了实现四种不同的栅极氧化物厚度，对所选择的第一生长氧化物和选择的第二生长氧化物区域进行氮化。 栅极氧化物的氮化还防止杂质掺杂剂跨过栅极氧化物层迁移并减少待机电流的泄漏。 该方法还减少由HF蚀刻剂引起的STI区域的拐角损失。

公开(公告)号：US07316970B2

公开(公告)日：2008-01-08

申请号：US10892014

申请日：2004-07-14

申请人： Chien-Hao Chen ,  Ju-Wang Hsu ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Ju-Wang Hsu ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/425

CPC分类号： H01L21/31111 ,  H01L21/823481 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78

摘要： A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for partially covering the original nitride layer. A wet etching is performed to remove the original nitride layer uncovered by the photoresist mask in such a way without causing substantial damage to the isolation structure. As such, the original nitride layer covered by the photoresist mask constitutes the resist protect layer.

摘要翻译： 在半导体衬底上形成抗蚀剂保护层的方法包括以下步骤。 在半导体衬底上形成隔离结构。 在半导体衬底上形成对隔离结构具有实质蚀刻选择性的原始氮化物层。 形成光致抗蚀剂掩模以部分覆盖原始氮化物层。 执行湿蚀刻以以这样的方式去除由光致抗蚀剂掩模未覆盖的原始氮化物层，而不会对隔离结构造成实质损坏。 因此，由光致抗蚀剂掩模覆盖的原始氮化物层构成抗蚀剂保护层。

公开(公告)号：US20060049470A1

公开(公告)日：2006-03-09

申请号：US10936271

申请日：2004-09-07

申请人： Chia-Lin Chen ,  Ming-Jie Huang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chia-Lin Chen ,  Ming-Jie Huang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/76

CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L29/665

摘要： A method for forming a microelectronic product and the microelectronic product resulting from the method both employ a bilayer gate electrode. The bilayer gate electrode employs: (1) a first layer formed of a random oriented polycrystalline silicon material; and (2) a second layer laminated to the first layer and formed of a columnar oriented polycrystalline silicon material. The gate electrode provides enhanced performance to a semiconductor device within which it is formed.

摘要翻译： 形成微电子产物的方法和由该方法得到的微电子产物都采用双层栅电极。 双层栅极采用：（1）由随机取向的多晶硅材料形成的第一层; 和（2）层压到第一层并由柱状取向的多晶硅材料形成的第二层。 栅电极为其形成的半导体器件提供增强的性能。

公开(公告)号：US20050242376A1

公开(公告)日：2005-11-03

申请号：US10834474

申请日：2004-04-29

申请人： Chien-Hao Chen ,  Chia-Lin Chen ,  Tze Lee ,  Shih-Chang Chen ,  Ju-Wang Hsu

发明人： Chien-Hao Chen ,  Chia-Lin Chen ,  Tze Lee ,  Shih-Chang Chen ,  Ju-Wang Hsu

IPC分类号： H01L21/336 ,  H01L21/338 ,  H01L21/76 ,  H01L29/745 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

摘要： A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant.

摘要翻译： 半导体器件包括衬底，设置在衬底上的栅极和形成在栅极两侧的衬底中的源极和漏极。 该器件还包括具有形成在栅极的侧壁上的第一层和第二层的薄间隔物，其中使用相同的蚀刻剂，第一层和第二层具有至少每分钟至少10埃的湿法蚀刻速率。

公开(公告)号：US07361572B2

公开(公告)日：2008-04-22

申请号：US11059728

申请日：2005-02-17

申请人： Chien-Hao Chen ,  Vincent S. Chang ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Vincent S. Chang ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/76

CPC分类号： H01L21/76235

摘要： A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of the trench surfaces using a nitrogen-containing gas prior to formation of the liner oxide layer, post-formation nitridation of the liner oxide layer, or both pre-treatment of the trench surfaces and post-formation nitridation of the liner oxide layer. The liner modification method of the present invention optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of STI structures and prevents diffusion of dopant into the liner oxide layer during subsequent processing.

摘要翻译： 公开了一种用于STI沟槽中的衬垫氧化物层的新的改进的衬垫修改方法。 根据该方法，在衬底中蚀刻STI沟槽，并且通过氧化技术在沟槽表面上形成衬垫氧化物层。 该方法还包括在形成衬垫氧化物层之前使用含氮气体预处理沟槽表面，衬里氧化物层的形成后氮化或沟槽表面的预处理和后形成氮化 的衬里氧化物层。 本发明的衬垫修改方法优化STI结构的反窄窄度效应（INWE）和栅极氧化物完整性（GOI），并防止掺杂剂在随后的处理期间扩散到衬里氧化物层中。

公开(公告)号：US07259050B2

公开(公告)日：2007-08-21

申请号：US10834474

申请日：2004-04-29

申请人： Chien-Hao Chen ,  Chia-Lin Chen ,  Tze Liang Lee ,  Shih-Chang Chen ,  Ju-Wang Hsu

发明人： Chien-Hao Chen ,  Chia-Lin Chen ,  Tze Liang Lee ,  Shih-Chang Chen ,  Ju-Wang Hsu

IPC分类号： H01L21/338

CPC分类号： H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

摘要： A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant.

摘要翻译： 半导体器件包括衬底，设置在衬底上的栅极和形成在栅极两侧的衬底中的源极和漏极。 该器件还包括具有形成在栅极的侧壁上的第一层和第二层的薄间隔物，其中使用相同的蚀刻剂，第一层和第二层具有至少每分钟至少10埃的湿蚀刻速率。

公开(公告)号：US07176138B2

公开(公告)日：2007-02-13

申请号：US10970090

申请日：2004-10-21

申请人： Chien-Hao Chen ,  Vincent S. Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

发明人： Chien-Hao Chen ,  Vincent S. Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

IPC分类号： H01L21/311

CPC分类号： H01L21/76232

摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.

摘要翻译： 一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI沟槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

公开(公告)号：US20060099771A1

公开(公告)日：2006-05-11

申请号：US10970090

申请日：2004-10-21

申请人： Chien-Hao Chen ,  Vincent Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

发明人： Chien-Hao Chen ,  Vincent Chang ,  Ji-Yi Yang ,  Chia-Lin Chen ,  Tze-Liang Lee

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.

摘要翻译： 一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。