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公开(公告)号：US06989331B2
公开(公告)日：2006-01-24
申请号：US10615558
申请日：2003-07-08
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.
摘要翻译： 从形成在下层上的图案化层去除硬掩模层的方法，其中使用蚀刻剂去除硬掩模层，当底层在通常需要的时间长时间暴露于蚀刻剂时不利地蚀刻下面的层 以去除硬掩模层，而不会有害地蚀刻下面的层。 修改硬掩模层，使得蚀刻剂以比蚀刻剂蚀刻下层的蚀刻剂快得多的速率蚀刻硬掩模层。 图案化硬掩模层。 蚀刻图案层以暴露下层的部分。 硬掩模层和下层的暴露部分用蚀刻剂蚀刻，其中蚀刻剂以比蚀刻剂蚀刻下层的速率快得多的速度蚀刻硬掩模层，这是因为硬的 掩模层。
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2.发明授权Method characterizing materials for a trench isolation structure having low trench parasitic capacitance 有权用于具有低沟槽寄生电容的沟槽隔离结构的方法表征材料公开(公告)号：US08021955B1
公开(公告)日：2011-09-20
申请号：US12574426
申请日：2009-10-06
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.
摘要翻译： 提供了用于在集成电路基板上形成多层隔离结构的方法和组合物。 工艺可以包括为下电介质层选择下电介质材料，并选择用于上电介质层的上电介质材料。 选择对应于下部和上部介电材料的厚度的一系列有效介电常数。 下介电层和上电介质层中的每一个的厚度范围由可接受的介电常数的范围决定，使用表示与下部上部电介质层的材料的厚度对应的有效介电常数的信息，能够形成多层电介质层， 层隔离结构。
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3.发明授权Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance 有权制造具有低沟槽寄生电容的浅沟槽隔离结构的方法公开(公告)号：US07001823B1
公开(公告)日：2006-02-21
申请号：US09991202
申请日：2001-11-14
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
摘要翻译： 提供了用于在集成电路基板上形成隔离结构的方法和组合物。 首先，在集成电路基板中蚀刻沟槽。 然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。 然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容 要减少
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4.发明授权公开(公告)号：US07619294B1
公开(公告)日：2009-11-17
申请号：US11262173
申请日：2005-10-28
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
摘要翻译： 提供了用于在集成电路基板上形成隔离结构的方法和组合物。 首先，在集成电路基板中蚀刻沟槽。 然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。 然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容 要减少
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公开(公告)号：US20050006347A1
公开(公告)日：2005-01-13
申请号：US10615558
申请日：2003-07-08
IPC分类号： H01L21/311 , C23F1/00
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.
摘要翻译： 从形成在下层上的图案化层去除硬掩模层的方法，其中使用蚀刻剂去除硬掩模层，当底层在通常需要的时间长时间暴露于蚀刻剂时不利地蚀刻下面的层 以去除硬掩模层，而不会有害地蚀刻下面的层。 修改硬掩模层，使得蚀刻剂以比蚀刻剂蚀刻下层的蚀刻剂快得多的速率蚀刻硬掩模层。 图案化硬掩模层。 蚀刻图案层以暴露下层的部分。 硬掩模层和下层的暴露部分用蚀刻剂蚀刻，其中蚀刻剂以比蚀刻剂蚀刻下层的速率快得多的速度蚀刻硬掩模层，这是因为硬的 掩模层。
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公开(公告)号：US08482990B2
公开(公告)日：2013-07-09
申请号：US13025872
申请日：2011-02-11
申请人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
发明人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C7/10
CPC分类号： G11C5/06 , G11C5/147 , G11C5/148 , G11C11/417
摘要： A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.
摘要翻译： 电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。 第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。
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公开(公告)号：US20080303278A1
公开(公告)日：2008-12-11
申请号：US11759243
申请日：2007-06-07
申请人： Ming-Yi Lee
发明人： Ming-Yi Lee
IPC分类号： F16L19/04
CPC分类号： F16L19/025 , F16L19/065
摘要： To couple a giving end of a first pipe and an receiving end of a second pipe, the device contains a rubber ring, a tubular screw, a C-shaped ring, and a rubber washer. The C-shaped ring is embedded in a groove of the giving end of the first pipe which is threaded through the rubber ring, the tubular screw and the rubber washer and is plugged into the receiving end of second pipe. Inside the tubular screw, the diameter is gradually shrunk to form a born-shaped space with a slant wall. When the tubular screw is screwed into the receiving end of the second pipe, the slant wall forces the C-shaped ring, and thereby the giving end of the first pipe, to gradually advance. In the mean time, the bottom of the tubular screw presses the rubber washer tightly against the second pipe to effectively prevent leakage.
摘要翻译： 为了连接第一管的给送端和第二管的接收端，该装置包含橡胶环，管状螺钉，C形环和橡胶垫圈。 C形环嵌入第一管的给出端的一个沟槽中，该沟槽穿过橡胶环，管状螺钉和橡胶垫圈，并被插入第二管的接收端。 在管状螺杆内部，直径逐渐收缩以形成具有倾斜壁的出生形状的空间。 当管状螺钉拧入第二管的接收端时，倾斜壁迫使C形环，从而使第一管的给出端逐渐前进。 同时，管状螺钉的底部将橡胶垫片紧紧地压在第二管上，以有效地防止泄漏。
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公开(公告)号：US06916700B1
公开(公告)日：2005-07-12
申请号：US10757519
申请日：2004-01-15
申请人： Yao-Sheng Huang , Hui-Lun Chen , Ming-Yi Lee
发明人： Yao-Sheng Huang , Hui-Lun Chen , Ming-Yi Lee
IPC分类号： H01L21/336 , H01L21/822 , H01L21/8242 , H01L27/06
CPC分类号： H01L27/0629
摘要： A mixed-mode process introduces a hard mask layer. Due to the introduced hard mask layer made of non-resist material formed over devices, performance of a formed capacitor is protected from effects of an implantation process such as source/drain implantation. A self-aligned silicide (salicide) process for a MOSFET transistor can also be performed. Thus, production efficiency and performance of an IC product formed by the mixed-mode process can be improved. Moreover, the number of required fabrication steps is reduced and cost savings can be realized.
摘要翻译： 混合模式工艺引入硬掩模层。 由于引入的由形成在器件上的非抗蚀剂材料制成的硬掩模层，所形成的电容器的性能被保护免于诸如源极/漏极注入的注入工艺的影响。 还可以执行用于MOSFET晶体管的自对准硅化物（自对准硅化物）工艺。 因此，可以提高由混合模式工艺形成的IC产品的生产效率和性能。 此外，减少了所需的制造步骤的数量并且可以实现成本节约。
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9.发明授权Apparatus and process for deposition of thin film on semiconductor substrate while inhibiting particle formation and deposition 失效用于在半导体衬底上沉积薄膜同时抑制颗粒形成和沉积的装置和方法
公开(公告)号：US6127286A
公开(公告)日：2000-10-03
申请号：US76502
申请日：1998-05-11
申请人： Kaijun Leo Zhang , Wilbur C. Catabay , Ming-Yi Lee
发明人： Kaijun Leo Zhang , Wilbur C. Catabay , Ming-Yi Lee
IPC分类号： C23C16/44 , C23C16/455 , H01L21/316 , H01L21/31 , H01L21/469
CPC分类号： C23C16/45572 , C23C16/4404 , C23C16/455 , H01L21/02164 , H01L21/02271 , H01L21/31612 , Y10S438/909
摘要： Gaseous reactants capable of depositing a thin film on a semiconductor substrate are introduced into a deposition zone of a deposition apparatus through a gaseous reactants dispersion apparatus having rounded corners and smoothed anodized surfaces and maintained at a temperature ranging from about 70.degree. C. to about 85.degree. C., and preferably from about 75.degree. C. to about 80.degree. C., to inhibit the deposition and accumulation on such surfaces of charged materials capable of generating particles which may cause damage to the semiconductor substrate.
摘要翻译： 能够在半导体衬底上沉积薄膜的气态反应物通过具有圆角和平滑阳极氧化表面的气态反应物分散装置引入沉积设备的沉积区，并保持在约70℃至约85℃ 并且优选约75℃至约80℃，以抑制能够产生可能引起半导体衬底损坏的颗粒的带电材料的这些表面上的沉积和积聚。
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公开(公告)号：US06737342B1
公开(公告)日：2004-05-18
申请号：US10458141
申请日：2003-06-09
申请人： Ming-Yi Lee , Chien-Hwa Chang
发明人： Ming-Yi Lee , Chien-Hwa Chang
IPC分类号： H01L21336
CPC分类号： H01L29/66477 , H01L29/6656 , H01L29/78
摘要： A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device having a gate oxide stack, followed by a low dielectric constant spacer layer. Anisotropic etching of the combined layers form spacers surrounding the gate oxide stack.
摘要翻译： 具有低重叠电容的复合间隔物的方法和组合物包括低k电介质间隔层。 第一间隔物沉积在具有栅极氧化物堆叠的部分形成的半导体器件上，随后是低介电常数间隔层。 组合层的各向异性蚀刻形成围绕栅极氧化物层的间隔物。
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